1st Edition

Nano-CMOS Gate Dielectric Engineering

By Hei Wong Copyright 2012
248 Pages 149 B/W Illustrations
by CRC Press

248 Pages 149 B/W Illustrations
by CRC Press

According to Moore’s Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT)... Read more

Overview of CMOS Technology
Introduction
MOS Transistor: A Quick Introduction to Classical Models
Short-Channel Effects and Short-Channel Modifications
Features and Uniqueness of MOS Transistor
MOS in Deca-Nanometer
Technology Trends and Options
Summary
References

High-k Dielectrics
The High-k Candidates
Electronic Structure of Transition Metals and Rare Earth Metals
Material Properties of Elemental Transition Metal and Rare Metal Oxides
Bandgap and Band Offset Energies
Bond Ionicity and Dielectric Constant
Carrier Effective Masses
Thermal Stability
Disorders and Defects
Summary
References

Complex Forms of High-k Oxides
Introduction
Silicates and Aluminates Pseudo-Binary Alloys
Stoichiometric Binary Alloys
Doping
Thermal Stability and Phase Separation
Summary
References

Dielectric Interfaces
Introduction
High-k/Silicon Interface
High-k/Metal Interface
Summary
References

Impacts on Device Operation
Introduction
Gate Leakage Current
Threshold Voltage Control and Fermi-Level Pinning
Channel Mobility
Subthreshold Characteristics
Dielectric Breakdown
Hot-Carrier Effects
Temperature Instabilities
Summary
References

Fabrication Issues
Process Integration
Atomic Layer Deposition
Metal Organic Chemical Vapor Deposition
Physical Vapor Deposition
Etching
Summary
References

Conclusions
Appendix A: Fundamental Physical Constants and Unit Conversions
Appendix B: Properties of Si and SiO2
Index

Biography

Hei Wong

... this book, by covering almost every aspect of high-k gate dielectric engineering for nano-CMOS technology, is as timely as ever for device and process engineers. Though it involves quite a lot of physics, it is never less than fascinating, through its many intuitive illustrations and tables.

—From the Foreword by Hiroshi Iwai, PhD, Professor, Tokyo Institute of Technology, Japan