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Asynchronous On-Chip Networks and Fault-Tolerant Techniques



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ISBN 9781032255750
April 25, 2022 Forthcoming by CRC Press
344 Pages 180 B/W Illustrations

 
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Book Description

This book is the first comprehensive study of fault-tolerance and fault-caused deadlock effects in asynchronous on-chip networks, aiming to overcome these drawbacks and ensure greater reliability of applications.
As a promising alternative to the widely used synchronous on-chip networks for multicore processors, asynchronous on-chip networks can be vulnerable to faults even if they can deliver the same performance with much lower energy and area compared with their synchronous counterparts - faults can not only corrupt data transmission but also cause a unique type of deadlock. By adopting a new redundant code along with a dynamic fault detection and recovery scheme, the authors demonstrate that asynchronous on-chip networks can be efficiently hardened to tolerate both transient and permanent faults and overcome fault-caused deadlocks.
This book will serve as an essential guide for researchers and students studying interconnection networks, fault tolerant computing, asynchronous system design, circuit design and on-chip networking, as well as for professionals interested in designing fault-tolerant and high-throughput asynchronous circuits.

Table of Contents

1. Introduction  2. Asynchronous Circuits  3. Asynchronous Networks-on-Chip  4. Optimizing Asynchronous On-Chip Networks  5. Fault-Tolerant Asynchronous Circuits  6. Fault-Tolerant Coding  7. Deadlock Detection  8. Deadlock Recovery  9. Summary

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Author(s)

Biography

Wei Song is Associate Professor in the State Key Laboratory of Information Security, Institute of Information Engineering, at Chinese Academy of Science, China. His current research focuses on the security of computer architectures.
Guangda Zhang is Associate Professor in the Defense Innovation Institute, at Academy of Military Sciences, China. His current research focuses on asynchronous circuit, microprocessor and computer architecture, and fault tolerance.