Designing Network On-Chip Architectures in the Nanoscale Era: 1st Edition (e-Book) book cover

Designing Network On-Chip Architectures in the Nanoscale Era

1st Edition

Edited by Jose Flich, Davide Bertozzi

Chapman and Hall/CRC

528 pages

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pub: 2019-08-30
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pub: 2010-12-18
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Going beyond isolated research ideas and design experiences, Designing Network On-Chip Architectures in the Nanoscale Era covers the foundations and design methods of network on-chip (NoC) technology. The contributors draw on their own lessons learned to provide strong practical guidance on various design issues.Exploring the design process of the

Table of Contents

NoC Technology. The Industrial Perspective. Upcoming Trends. Appendix. Bibliography.

About the Editors

Jose Flich is an associate professor of computer architecture and technology at the Technical University of Valencia. Dr. Flich is the coordinator of the EU-funded NaNoC project; co-chair of the CAC, CASS, and INA-OCMC workshops; and co-developer of RECN, the only truly scalable congestion management technique proposed to date. He is also associate editor of the IEEE Transactions on Parallel and Distributed Systems. His research interests include high-performance interconnection networks for multiprocessor systems, clusters of workstations, and networks on-chip.

Davide Bertozzi is an assistant professor and leader of the Multi-Processor Systems-On-Chip research group at the University of Ferrara. Dr. Bertozzi is the general chair of the INA-OCMC workshop and an editorial board member of IET Computers & Digital Techniques. His research interests encompass multi-core digital integrated systems, with an emphasis on all aspects of system interconnect design.

Subject Categories

BISAC Subject Codes/Headings:
COMPUTERS / Systems Architecture / General
COMPUTERS / Programming / Games
COMPUTERS / Computer Engineering
TECHNOLOGY & ENGINEERING / Electronics / Circuits / General
TECHNOLOGY & ENGINEERING / Electronics / Microelectronics