Energy-Aware Memory Management for Embedded Multimedia Systems: A Computer-Aided Design Approach presents recent computer-aided design (CAD) ideas that address memory management tasks, particularly the optimization of energy consumption in the memory subsystem. It explains how to efficiently implement CAD solutions, including theoretical methods and novel algorithms.
The book covers various energy-aware design techniques, including data-dependence analysis techniques, memory size estimation methods, extensions of mapping approaches, and memory banking approaches. It shows how these techniques are used to evaluate the data storage of an application, reduce dynamic and static energy consumption, design energy-efficient address generation units, and much more.
Providing an algebraic framework for memory management tasks, this book illustrates how to optimize energy consumption in memory subsystems using CAD solutions. The algorithmic style of the text should help electronic design automation (EDA) researchers and tool developers create prototype software tools for system-level exploration, with the goal to ultimately obtain an optimized architectural solution of the memory subsystem.
Table of Contents
Computer-Aided Design for the Energy Optimization in the Memory Architecture of Embedded Systems, Florin Balasa and Dhiraj K. Pradhan
Low-Power Design for Embedded Systems
The Role of On-Chip Memories
Optimization of the Energy Consumption of the Memory Subsystem
The Goal and Organization of the Book
The Power of Polyhedra, Doran K. Wilde
Representation of Polyhedra in a Computer
Description of Operations
Loop Nest Synthesis Using Polyhedral Operations
Localizing Affine Dependences
Computation of Data Storage Requirements for Affine Algorithmic Specifications, Florin Balasa, Hongwei Zhu, and Ilie I. Luican
The Memory Size Computation Problem: A Brief Overview
Computation of the Minimum Data Storage for Affine Specifications
Operations with Linearly Bounded Lattices
Computation of the Minimum Data Storage
Polyhedral Techniques for Parametric Memory Requirement Estimation, Philippe Clauss, Diego Garbervetsky, Vincent Loechner, and Sven Verdoolaege
The Polyhedral Model of Loop Nests
Counting the Elements in a Polyhedral Set
Memory Requirement Estimates Based on Maximization Problems
Storage Allocation for Streaming-Based Register File, Praveen Raghavan and Francky Catthoor
Stream Register File: Why and How
Model for Compilation on Stream Register File
SARA: StreAm-Register-Allocation-Based Compilation
Optimization of the Dynamic Energy Consumption and Signal Mapping in Hierarchical Memory Organizations, Florin Balasa, Ilie I. Luican, Hongwei Zhu, and Doru V. Nasui
Energy-Aware Signal Assignment to the Memory Layers
Signal-to-Memory Mapping Techniques
The Signal-to-Memory Mapping Model
Leakage Current Mechanisms and Estimation in Memories and Logic, Ashoka Sathanur, Praveen Raghavan, Stefan Cosemans, and Wim Dahaene
Leakage Current Mechanisms
Power Breakdown in SoCs
Leakage Current Modeling and Estimation
Leakage Control in SoCs, Praveen Raghavan, Ashoka Sathanur, Stefan Cosemans, and Wim Dahaene
Leakage Power Reduction Techniques
Leakage Power Reduction Techniques Applied to SRAM Memories
Leakage Power Reduction Using Low Power EDA Flows
Compiler-Driven Leakage Power Reduction
Energy-Efficient Memory Port Assignment, Preeti Ranjan Panda and Lakshmikantam Chitturi
Memory Energy-Aware Synthesis
Energy-Efficient Address-Generation Units and Their Design Methodology, Ittetsu Taniguchi, Guillermo Talavera, and Francky Catthoor
Motivation behind Exploration of AGUs
Reconfigurable AGU: What Do We Execute the Calculations on?
Architecture Exploration Problem: What Is the Optimal Solution?
AGU Mapping Framework: How Is the Address Calculation Mapped on the AGU Model?
AGU Exploration Framework: How Are Pareto Solutions Obtained from the Solution Space?
Conclusion and Future Work
References appear at the end of each chapter.
Florin Balasa is an associate professor in the Department of Computer Science and Engineering at the American University in Cairo. A senior member of IEEE, Dr. Balasa holds two patents and is an associate editor of the International Journal of Computers and Electrical Engineering. He has also been a recipient of a National Science Foundation CAREER Award. His research focuses on algorithms and software systems for VLSI design automation.
Dhiraj K. Pradhan is a chair and professor in the Department of Computer Science at the University of Bristol. A fellow of ACM, IEEE, and the Japan Society of Promotion of Science, Dr. Pradhan holds two patents and has been a recipient of the Humboldt Prize and Fulbright-Flad Chair in Computer Science. For more than thirty years, his research has focused on VLSI computer-aided design and testing as well as fault-tolerant computing, computer architecture, and parallel processing.