Multi-Core Embedded Systems: 1st Edition (Hardback) book cover

Multi-Core Embedded Systems

1st Edition

Edited by Georgios Kornaros

CRC Press

502 pages | 205 B/W Illus.

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Hardback: 9781439811610
pub: 2010-04-07
eBook (VitalSource) : 9781315218199
pub: 2018-10-08
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Details a real-world product that applies a cutting-edge multi-core architecture

Increasingly demanding modern applications—such as those used in telecommunications networking and real-time processing of audio, video, and multimedia streams—require multiple processors to achieve computational performance at the rate of a few giga-operations per second. This necessity for speed and manageable power consumption makes it likely that the next generation of embedded processing systems will include hundreds of cores, while being increasingly programmable, blending processors and configurable hardware in a power-efficient manner.

Multi-Core Embedded Systems presents a variety of perspectives that elucidate the technical challenges associated with such increased integration of homogeneous (processors) and heterogeneous multiple cores. It offers an analysis that industry engineers and professionals will need to understand the physical details of both software and hardware in embedded architectures, as well as their limitations and potential for future growth.

Discusses the available programming models spread across different abstraction levels

The book begins with an overview of the evolution of multiprocessor architectures for embedded applications and discusses techniques for autonomous power management of system-level parameters. It addresses the use of existing open-source (and free) tools originating from several application domains—such as traffic modeling, graph theory, parallel computing and network simulation. In addition, the authors cover other important topics associated with multi-core embedded systems, such as:

  • Architectures and interconnects
  • Embedded design methodologies
  • Mapping of applications
  • Programming paradigms and models of computation
  • Power optimization and reliability issues
  • Performance tools and benchmarks
  • Resource management
  • Multithreading
  • Multi-core programming challenges
  • Compiler and operating system support

This is a detailed discussion of research on the interaction between multi-core systems, applications and software views, and processor configuration and extension, which add a new dimension to the problem space. The text offers a useful overview of the most widespread industrial and domain-specific solutions, providing several examples of working implementations.

Table of Contents

Multi-Core Architectures for Embedded Systems, C.P. Ravikumar

Architectural Considerations

Interconnection Networks

Software Optimizations

Application-Specific Customizable Embedded Systems, G. Kornaros

Challenges and Opportunities


Configurable Processors and Instruction Set Synthesis

Reconfigurable Instruction Set Processors

Hardware/Software Co-design

Hardware Architecture Description Languages

Myths and Realities

Case Study: Realizing Customizable Multi-Core Designs

The Future: System Design with Customizable Architectures, Software, and Tools

Power Optimization in Multi-Core System-on-Chip, M. Conti, S. Orcioni, G. Vece and S. Gigli

Low Power Design


On-Chip Communication Architectures


DPM and DVS in Multi-Core Systems

Routing Algorithms for Irregular Mesh-based Network-on-Chip, S.-Y. Lin and A.-Y. (Andy) Wu

An Overview of Irregular Mesh Topology

Fault-Tolerant Routing Algorithms for 2D Meshes

Routing Algorithms for Irregular Mesh Topology

Placement for Irregular Mesh Topology

Hardware Efficient Routing Algorithm

Debugging Multi-Core Systems-on-Chip, B. Vermeulen and K. Goossens

Why Debugging is Difficult

Debugging an SoC

Debug Methods

CSAR Debug Approach

On-Chip Debug Infrastructure

Off-Chip Debug Infrastructure

Debug Example

System-level Tools for NoC-based Multi-Core Design, L. Bononi, N. Concer, and M. Grammatikakis

Synthetic Traffic Models

Graph Theoretical Analysis

Task Mapping for SoC Applications

OMNeT++ Simulation Framework

A Case Study

Compiler Techniques for Application Level Memory Optimization, B. Girodias, Y. Bouchebaba, P. Paulin, B. Lavigueur, G. Nicolescu, and E.M. Aboulhamid

Loop Transformation for Single and Multiprocessors

Program Transformation Concepts

Memory Optimization Techniques

MPSoC Memory Optimization Techniques

Technique Impacts

Improvement in Optimization Techniques

Programming Models for Multi-Core Embedded Software, B.A. Jose, B. Xue, S.K. Shukla and J.-P. Talpin

Thread Libraries for Multi-threaded Programming

Protections for Data Integrity in a Multi-threaded Environment

Programming Models for Shared Memory and Distributed Memory

Parallel Programming on Multiprocessors

Parallel Programming Using Graphic Processors

Model-driven Code Generation for Multi-Core Systems

Synchronous Programming Languages

Imperative Synchronous Language: Esterel

Declarative Synchronous Language: LUSTRE

Multi-Rate Synchronous Language: SIGNAL

Programming Models for Real-Time Software

Future Directions for Multi-Core Programming

Operating System Support for Multi-Core Systems-on-Chips, X. Gu´erin and F. P´etrot

Ideal Software Organization

Programming Challenges

General Approach

Real-Time and Component-based Operating System Models

Pros and Cons

Autonomous Power Management in Embedded Multi-Cores, A. Mukherjee, A. Ravindran, B.K. Joshi, K. Datta, and Y. Liu

Survey of Autonomous Power Management Techniques

Power Management and RTOS

Power-Smart RTOS and Processor Simulators

Autonomous Power Saving in Multi-Core Processors

Power Saving Algorithms

Multi-Core System-on-Chip in Real World Products, G. Panesar, A. Duller, A.H. Gray and D. Towner

Overview of picoArray Architecture

Tool Flow

picoArray Debug and Analysis

Hardening Process in Practice

Design Example

Embedded Multi-Core Processing for Networking, T. Orphanoudakis and S. Perissakis

Overview of Proposed NPU Architectures

Programmable Packet Processing Engines

Address Lookup and Packet Classification Engines

Packet Buffering and Queue Management Engines

Scheduling Engines


About the Editor

Georgios Kornaros is currently with the Applied Informatics and Multimedia Department of the Technological Educational Institute of Crete in Greece and also with the Technical University of Crete, Greece. In the past he worked as a systems architect and designer of single-chip switches and network processor designs for a few research institutes and companies. Kornaros has taped out three single-chip multi-core devices for networking. As a technical manager of the Digital Integrated Systems Group of ISD SA (2000) and later, also as Technical Manager of Ellemedia Technologies Ltd. Crete Department (2001-2005), he designed a few network processors. His research interests include high-speed communication architectures, networking systems, multi-core architectures, embedded and reconfigurable systems, full and semi-custom IC design. Kornaros is the author or co-author of more than 40 publications in refereed international conferences and journals. He is an IEEE member and a member of the Technical Chamber of Greece.

About the Series

Embedded Multi-Core Systems

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Subject Categories

BISAC Subject Codes/Headings:
COMPUTERS / Computer Engineering
TECHNOLOGY & ENGINEERING / Electronics / Microelectronics