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Multi-Core Embedded Systems





ISBN 9781439811610
Published April 7, 2010 by CRC Press
502 Pages

 
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Book Description

Details a real-world product that applies a cutting-edge multi-core architecture



Increasingly demanding modern applications—such as those used in telecommunications networking and real-time processing of audio, video, and multimedia streams—require multiple processors to achieve computational performance at the rate of a few giga-operations per second. This necessity for speed and manageable power consumption makes it likely that the next generation of embedded processing systems will include hundreds of cores, while being increasingly programmable, blending processors and configurable hardware in a power-efficient manner.





Multi-Core Embedded Systems presents a variety of perspectives that elucidate the technical challenges associated with such increased integration of homogeneous (processors) and heterogeneous multiple cores. It offers an analysis that industry engineers and professionals will need to understand the physical details of both software and hardware in embedded architectures, as well as their limitations and potential for future growth.





Discusses the available programming models spread across different abstraction levels





The book begins with an overview of the evolution of multiprocessor architectures for embedded applications and discusses techniques for autonomous power management of system-level parameters. It addresses the use of existing open-source (and free) tools originating from several application domains—such as traffic modeling, graph theory, parallel computing and network simulation. In addition, the authors cover other important topics associated with multi-core embedded systems, such as:









  • Architectures and interconnects








  • Embedded design methodologies








  • Mapping of applications






Table of Contents

Multi-Core Architectures for Embedded Systems, C.P. Ravikumar. Application-Specific Customizable Embedded Systems, G. Kornaros. Power Optimization in Multi-Core System-on-Chip, M. Conti, S. Orcioni, G. Vece and S. Gigli. Routing Algorithms for Irregular Mesh-based Network-on-Chip, S.-Y. Lin and A.-Y. (Andy) Wu. Debugging Multi-Core Systems-on-Chip, B. Vermeulen and K. Goossens. System-level Tools for NoC-based Multi-Core Design, L. Bononi, N. Concer, and M. Grammatikakis. Compiler Techniques for Application Level Memory Optimization, B. Girodias, Y. Bouchebaba, P. Paulin, B. Lavigueur, G. Nicolescu, and E.M. Aboulhamid. 8 Programming Models for Multi-Core Embedded Software, B.A. Jose, B. Xue, S.K. Shukla and J.-P. Talpin. Operating System Support for Multi-Core Systems-on-Chips, X. Gu´erin and F. P´etrot. Autonomous Power Management in Embedded Multi-Cores, A. Mukherjee, A. Ravindran, B.K. Joshi, K. Datta, and Y. Liu. Multi-Core System-on-Chip in Real World Products, G. Panesar, A. Duller, A.H. Gray and D. Towner. Embedded Multi-Core Processing for Networking, T. Orphanoudakis and S. Perissakis. Index.

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Editor(s)

Biography

Georgios Kornaros is currently with the Applied Informatics and Multimedia Department of the Technological Educational Institute of Crete in Greece and also with the Technical University of Crete, Greece. In the past he worked as a systems architect and designer of single-chip switches and network processor designs for a few research institutes and companies. Kornaros has taped out three single-chip multi-core devices for networking. As a technical manager of the Digital Integrated Systems Group of ISD SA (2000) and later, also as Technical Manager of Ellemedia Technologies Ltd. Crete Department (2001-2005), he designed a few network processors. His research interests include high-speed communication architectures, networking systems, multi-core architectures, embedded and reconfigurable systems, full and semi-custom IC design. Kornaros is the author or co-author of more than 40 publications in refereed international conferences and journals. He is an IEEE member and a member of the Technical Chamber of Greece.