1st Edition

Quantum-Dot Cellular Automata Circuits for Nanocomputing Applications

    252 Pages 47 Color & 159 B/W Illustrations
    by CRC Press

    252 Pages 47 Color & 159 B/W Illustrations
    by CRC Press

    This book provides a composite solution for optimal logic designs for Quantum-Dot Cellular Automata based circuits. It includes the basics of new logic functions and novel digital circuit designs, quantum computing with QCA, new trends in quantum and quantum-inspired algorithms and applications, and algorithms to support QCA designers.

    Futuristic Developments in Quantum-Dot Cellular Automata Circuits for Nanocomputing includes QCA-based new nanoelectronics architectures that help in improving the logic computation and information flow at physical implementation level. The book discusses design methodologies to obtain an optimal layout for some of the basic logic circuits considering key metrics such as wire delays, cell counts, and circuit area that help in improving the logic computation and information flow at physical implementation level. Examines several challenges toward QCA technology like clocking mechanism, floorplan which would facilitate manufacturability, Electronic Design Automation (EDA) tools for design and fabrication like simulation, synthesis, testing etc.

    The book is intended for students and researchers in electronics and computer disciplines who are interested in this rapidly changing field under the umbrella of courses such as emerging nanotechnologies and its architecture, low-power digital design. The work will also help the manufacturing companies/industry professionals, in nanotechnology and semiconductor engineers in the development of low power quantum computers.

    Chapter 1. Towards The Evaluation from Low Power VLSI to Quantum Circuits. Deepak Garg and Devendra Kumar Sharma.

    Chapter 2. Investigations on Designing of Adders, Multiplexers and Flip-Flops for Fast Memories Development in QCA Technology. Paramjeet, Saptarshi Gupta, and Hari Mohan Gaur.

    Chapter 3. An optimized approach of Designing Adders and Multiplexer in QCA. Vaibhav Jaina, Devendra Kumar Sharma and Hari Mohan Gaur.

    Chapter 4. High-Speed Comparator and Parity Generator towards simplified clocking circuit in QCA Technology. Trailokya Nath Sasamal, Hari Mohan Gaur, Vineet Jaiswal, Gaurav Saini and Ashutosh Kumar Singh.

    Chapter 5. Towards Effective Multiplexer Circuit Design in QCA Technology. Abdalhossein Rezai1, Davood Aliakbari, Asghar Karimi and Sasan Ansarian Najafabadi.

    Chapter 6. An optimized approach of Designing Register and Counter in QCA. Vaibhav Jain, Devendra Kumar Sharma and Hari Mohan Gaur.

    Chapter 7. QCA-based Designs of Majority Gates, Flip-Flops and Polar Encoders. Aibin Yan, Aoran Cao, Runqi Liu and Xuehua Li.

    Chapter 8. Physically realizable Reversible logic gates in beyond CMOS QCA Technology. Lakshminarayanan Gopalakrishnan, Marshal R , Raja Sekar K, Seok-Bum Ko and Anantharaj Thalaimalai Vanaraj.

    Chapter 9. Design of new circuits for Reversible ALU in QCA Technology. Saeed Ghorbani Rizi, Abdalhossein Rezai and Hamid Mahmoodian.

    Chapter 10. Stick Diagram Representation for MQCA-based Multiplexer. Vineet Jaiswal and Trailokya Nath Sasamal.

    Chapter 11. Fully Depleted Planar bi-layer Junctionless Transistor for Future Technology Node. Gaurav Saini and Trailokya Nath Sasamal. Index.


    Dr. Trailokya Nath Sasamal is currently working as Assistant Professor in the Department of Electronics & Communication Engineering at National Institute of Technology, Kurukshetra, India since August 2013. He has more than 11 years research and teaching experience in various University systems of India. Dr. Sasamal has obtained Ph.D. degree from the Department of Electronics & Communication Engineering, NIT Kurukshetra, Haryana. He obtained his M. Tech degree in Electronics Engineering from Indian Institute of Technology, Banaras Hindu University, Varanasi, India. He obtained his B. Tech degree in Electronics & Telecommunication from the KEC, Bhubaneswar, India, in 2007. He has presented and published over 60 research papers in reputed journals and various national and international conferences. His research interests include Quantum-dot Cellular Automata, Reversible logic, and new architectures for emerging nano-devices. He is the author of the book "Quantum-Dot Cellular Automata Based Digital Logic Circuits: A Design Perspective", published in Springer. He is also involved in reviewing processes in different journals and conferences such as; IEEE, IET, JCSC, IETE, DSJ etc.

    Dr. Hari Mohan Gaur is currently working with the School of Computer Science Engineering and Technology at Bennett University, Greater Noida, India. He obtained Ph.D from National Institute of Technology Kurukshetra (NIT-KKR) in Reversible and Quantum Computation. Hari Mohan Gaur has more than 15 years of experience in academic, research and administrative capacities. He is a distinguished Researcher, well known in Academic Fraternity for his interdisciplinary research in the areas of Quantum Computation, Fault Tolerant Digital Design, IOT and Data Security in Cloud Environment. Dr. Gaur holds the credit of contribution in several quality research journals of international repute published by IEEE, ACM, IET, Elsevier, etc. He is having a wide exposure of handling research proposals, international conferences, Training and Faculty Development Programs. He is involved in a joint research group involving eminent professors from top universities of US, UK, Japan, Taiwan and Malaysia. He has also been editor and reviewer of several international journals and is a member of IEEE since 2017.

    Prof. Ashutosh Kumar Singh is an esteemed researcher and academician in the domain of Electrical and Computer engineering. Currently, he is working as a Professor; Department of Computer Applications; National Institute of Technology; Kurukshetra, India. He has more than 20 years research, teaching and administrative experience in various University systems of the India, UK, Australia and Malaysia. Dr. Singh obtained his Ph. D. degree in Electronics Engineering from Indian Institute of Technology-BHU, India; Post Doc from Department of Computer Science, University of Bristol, United Kingdom and Charted Engineer from United Kingdom. He is the recipient of Japan Society for the Promotion of Science (JSPS) fellowship for visit in University of Tokyo and other universities of Japan. His research area includes Verification, Synthesis, Design and Testing of Digital Circuits, Predictive Data Analytics, Data Security in Cloud, Web Technology. He has more than 350 publications till now which includes peer reviewed journals, books, conferences, book chapters and news magazines in these areas. He has co-authored eight books including "Web Spam Detection Application using Neural Network", "Digital Systems Fundamentals" and "Computer System Organization & Architecture". Prof. Singh has worked as principal investigator/investigator for six sponsored research projects and was a key member on a project from EPSRC (United Kingdom) entitled "Logic Verification and Synthesis in New Framework". Dr. Singh has visited several countries including Australia, United Kingdom, South Korea, China, Thailand, Indonesia, Japan and USA for collaborative research work, invited talks and to present his research work. He had been entitled for 15 awards such as Merit Awards-2003 (Institute of Engineers), Best Poster Presenter-99 in 86th Indian Science Congress held in Chennai, INDIA, Best Paper Presenter of NSC’99 INDIA and Bintulu Development Authority Best Postgraduate Research Paper Award for 2010, 2011, 2012.

    Prof. Xiaoqing Wen (Fellow, IEEE) received the B.E. degree from Tsinghua University, China, in 1986, the M.E. degree from Hiroshima University, Japan, in 1990, and the Ph.D. degree from Osaka University, Japan, in 1993. From 1993 to 1997, he was an Assistant Professor at Akita University, Japan. He was a Visiting Researcher at the University of Wisconsin, Madison, USA, from October 1995 to March 1996. He joined SynTest Technologies, Inc., USA, in 1998, and served as its Chief Technology Officer until 2003. In 2004, he joined the Kyushu Institute of Technology, Japan, where he is currently a Professor and the Chair of the Department of Creative Informatics. He founded the Dependable Integrated Systems Research Center in 2015 and served as its Director until 2017. He has co-authored and co-edited two books: VLSI Test Principles and Architectures: Design for Testability (Morgan Kaufmann, 2006) and Power-Aware Testing and Test Strategies for Low Power Devices (Springer, 2009). He holds 43 U.S. patents and 14 Japanese patents on VLSI testing. His research interests include VLSI test, diagnosis, and testable design. He is a member of the IEICE, the IPSJ, and the REAJ. He received the 2008 IEICE-ISS Best Paper Award for his pioneering work on X-filling-based low-capture-power test generation. He has/is served/serving as an Associate Editor for the IEEE Transactions on Computer- Aided Design, the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, and the Journal of Electronic Testing: Theory and Applications