1st Edition

Reconfigurable Computing Systems Engineering
Virtualization of Computing Architecture

ISBN 9781439856215
Published May 24, 2016 by CRC Press
320 Pages - 18 Color & 114 B/W Illustrations

USD $140.00

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Book Description

Reconfigurable Computing Systems Engineering: Virtualization of Computing Architecture describes the organization of reconfigurable computing system (RCS) architecture and discusses the pros and cons of different RCS architecture implementations. Providing a solid understanding of RCS technology and where it’s most effective, this book:

  • Details the architecture organization of RCS platforms for application-specific workloads
  • Covers the process of the architectural synthesis of hardware components for system-on-chip (SoC) for the RCS
  • Explores the virtualization of RCS architecture from the system and on-chip levels
  • Presents methodologies for RCS architecture run-time integration according to mode of operation and rapid adaptation to changes of multi-parametric constraints
  • Includes illustrative examples, case studies, homework problems, and references to important literature

A solutions manual is available with qualifying course adoption.

Reconfigurable Computing Systems Engineering: Virtualization of Computing Architecture offers a complete road map to the synthesis of RCS architecture, exposing hardware design engineers, system architects, and students specializing in designing FPGA-based embedded systems to novel concepts in RCS architecture organization and virtualization.

Table of Contents

Introduction to Reconfigurable Computing Systems
Computational Process and Classification of Computing Architectures
Formal Definition of Computing Architecture
Correspondence between the Task and the Computing Architecture
Concept of a Computing System with a Programmable Procedure
Concept of an Application-Specific Computing System
Concept of the Computing System with Programmable Architecture
Organization of RCS and Major Components of the RCS Architecture
Exercises and Problems

Organization of the Field of Configurable Resources
Granularity of Logic Elements for the FCR
Heterogeneous Organization of the FCR
Dynamic versus Static Reconfiguration of Resources in FCR
Spatial versus Temporal Partitioning of Resources in an FCR
Exercises and Problems

Architecture of the On-Chip Processing Elements
Architecture of the Fine-Grained Configurable Processing Elements
Architecture of the Coarse-Grained Configurable Processing Elements
Architecture of the Hybrid Programmable Processing Elements
Exercises and Problems

Reconfigurable Communication Infrastructure in the FCR
Organization of the On-Chip Communication Infrastructure
Fine-Grained On-Chip Routing Elements in the FCR
Coarse-Grained On-Chip Routing Elements in the FCR
Fine-Grained On-Chip Configurable Input/Output Elements
Generic Organization of Input and Output Buffers for PCB Interface
Generic Organization of Output Buffers for Dynamic Links (Buses)
Reduction of Electromagnetic Noise and Crosstalk in Data Transfer Lines
Increasing Bandwidth Using DDR Transmission
Coarse-Grained Interface Elements for On-Board Communication
Exercises and Problems

System-Level Organization of the FCR
FCR Organization Based on Static Links between PLD-Nodes
Organization of Dynamic System-Level Network in the Multi-PLD FCR
Organization of the Hybrid FCR with Programmable Processing Units
Organization of the Multiboard Communication Network
Exercises and Problems

Configuration Memory and Architecture Virtualization in RCS
Generic Organization of Configuration Memory Hierarchy in the RCS
Concept of Virtualization of Hardware Resources in the RCS
Exercises and Problems

Reconfiguration Process Organization in the On-Chip Level of a Reconfigurable Computing System
Reconfiguration of the On-Chip Resources in the RCS
Partitioning the On-Chip Field of Configurable Resources
Partitioning the On-Chip Configuration Memory for Partial Reconfiguration
Reconfiguration Process and Configuration Bit-File Structure
Configuration of Port and Bus Organization and Reconfiguration Time
Self-Reconfiguration of the On-Chip FCR and On-Chip Configuration Port
Organization of the On-Chip Configuration Cache Memory
Organization of the Internal Configuration Controller-Loader
Exercises and Problems

RCS Architecture Configuration and Runtime Reconfiguration
Methods of Start-Up Configuration of the FCR at System Level
Serial Daisy-Chain Configuration Scheme
Serial and Parallel Ganged Configuration of Multiple PLDs
Parallel Daisy-Chain Configuration Scheme
Parallel Passive Configuration Scheme
Multibus Configuration Scheme for Multiple PLDs
Preconfiguration of Single or Multiple PLDs
Organization of Runtime Reconfiguration of the FCR at a System Level
Multiboot Runtime Self-Reconfiguration of Single and Multiple PLDs
Multiboot Runtime Reconfiguration with Distributed External Control
Multiboot Runtime Reconfiguration with Centralized External Control
Partial Runtime Reconfiguration with Centralized External Control
Partial Runtime Reconfiguration with Distributed Control
Exercises and Problems

Virtualization of the Architectural Components of a System on Chip
General Organization of the Task Execution Process
Segmentation of a Task and Concept of Functional Segment
Segmentation according to Specification and Performance Requirements
Segmentation according to Mode-Switching Time and System Constrains
Implementation of Functional Segments in the Form of Virtual Components
Computation Acceleration Exploiting Different Sources of Parallelism
Computation Acceleration Using Pipelined Processing Circuits
Computation Acceleration Exploiting Control-Flow Parallelism
Computation Acceleration by Proper Resource Binding
Computation Acceleration Using Data Structure Segmentation
Organization of the Virtual Hardware Component
Exercises and Problems

Virtualization of Reconfigurable Computing System Architecture
General Organization of the RCS Architecture
Concept of ASVP and Hardware Components Integration
ASVP with Statically Integrated Hardware Components
ASVP with Dynamically Integrated Software and Hardware Components
ASVP with Temporarily Integrated Hardware Components
ASVP with Spatially Integrated Hardware Components
Exercises and Problems

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Lev Kirischian, Ph.D, P.Eng, Member IEEE, has been affiliated with Ryerson University, Canada for 18 years. His research involves dynamically reconfigurable computing systems, automated architectural synthesis of data-stream processors, and workload-adaptive and self-healing reconfigurable architectures. He participated in the research and development of the first-generation Soviet supercomputers with reconfigurable architectures in the 1980s, FPGA-based segment of COFDM modulation technology for digital audio/video broadcasting systems for satellite and terrestrial networks (used in the SiriusXM satellite radio network), workload adaptive and self-restorable space-borne embedded computer platforms, and 3D-panoramic machine vision systems, among other technologies. In the last decade, he has developed and taught several courses associated with high-performance and reconfigurable computing as well as high-level synthesis of application-specific processors.


"Other texts having a similar focus tend to become entangled in technical details relating to a particular programming language, set of computer aided design tools, or device technology. As a result, these texts usually have a relatively short shelf life before they become obsolete. This text, on the other hand, is unique in that it stays within the realm of concepts and top-level design analysis and methodology, allowing it to be, and remain, applicable and relevant over a wide range of technologies."
—Dr. Jason D. Bakos, University of South Carolina, Columbia, USA

"The systematic representation of material, the detailed discussion of the main concepts, and the analysis of pros/cons of different approaches in architecture virtualization and static and dynamic integration will make this book very useful for engineers and students specializing in the development and design of field-programmable gate array (FPGA)-based reconfigurable computing systems."
—From the Foreword by Dr. Karen Safaryan, Vice President and Chief Technology Officer, Unique Broadband Systems, Ltd. and Director of R&D and Engineering, UBS-Axcera, Inc. Canada