Advances in design methods and process technologies have resulted in a continuous increase in the complexity of integrated circuits (ICs). However, the increased complexity and nanometer-size features of modern ICs make them susceptible to manufacturing defects, as well as performance and quality issues. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits covers common problems in areas such as process variations, power supply noise, crosstalk, resistive opens/bridges, and design-for-manufacturing (DfM)-related rule violations. The book also addresses testing for small-delay defects (SDDs), which can cause immediate timing failures on both critical and non-critical paths in the circuit.
- Overviews semiconductor industry test challenges and the need for SDD testing, including basic concepts and introductory material
- Describes algorithmic solutions incorporated in commercial tools from Mentor Graphics
- Reviews SDD testing based on "alternative methods" that explores new metrics, top-off ATPG, and circuit topology-based solutions
- Highlights the advantages and disadvantages of a diverse set of metrics, and identifies scope for improvement
Written from the triple viewpoint of university researchers, EDA tool developers, and chip designers and tool users, this book is the first of its kind to address all aspects of SDD testing from such a diverse perspective. The book is designed as a one-stop reference for current industrial practices, research challenges in the domain of SDD testing, and recent developments in SDD solutions.
Table of Contents
Fundamentals of Small-Delay Defect Testing
Sudhakar M. Reddy and Peter Maxwell
K Longest Paths
Duncan M. (Hank) Walker
Mark Kassab, Benoit Nadeau-Dostie, and Xijiang Lin
Faster-than-at-Speed Test for Screening Small-Delay Defects
Nisar Ahmed and Mohammad Tehranipoor
Circuit Path Grading Considering Layout, Process Variations, and Cross Talk
Ke Peng, Mahmut Yilmaz, and Mohammad Tehranipoor
Output Deviations-Based SDD Testing
Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay Defects
Sandeep K. Goel and Narendra Devta-Prasanna
Circuit Topology-Based Test Pattern Generation for Small-Delay Defects
Sandeep K. Goel and Krishnendu Chakrabarty
Small-Delay Defect Coverage Metrics
Narendra Devta-Prasanna and Sandeep K. Goel
Sandeep Kumar Goel is a Senior Manager (DFT/3D-Test) with Taiwan Semiconductor Manufacturing Company (TSMC), San Jose, CA. He received his Ph.D. degree from the University of Twente, The Netherlands. Prior to TSMC, he was in various research and management positions with LSI Corporation CA, Magma Design Automation, CA, and Philips Research, The Netherlands. He has co-authored two books, three book chapters, and published over 80 papers in journals and conference/workshop proceedings. He has delivered several invited talks and has been panelist at several conferences. He holds 15 U.S. and 5 European patents and has over 30 other patents pending. His current research interests include all topics in the domain of testing, diagnosis and failure analysis of 2D/3D chips. Dr. Goel was a recipient of the Most Significant Paper Award at the IEEE International Test Conference in 2010. He serves on various conference committees including DATE, ETS, ITC, DATA, and 3DTest. He was the General Chair of 3D Workshop at DATE 2012. He is a senior member of the IEEE.
Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, as well as M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively. He is now Professor of Electrical and Computer Engineering at Duke University. He is also a Chair Professor of Software Theory in the School of Software, Tsinghua University, Beijing, China. Dr. Chakrabarty is a recipient of the National Science Foundation Early Faculty (CAREER) award, the Office of Naval Research Young Investigator award, the Humboldt Research Fellowship, and several best papers awards at IEEE conferences.