This book aims to highlight the research activities in the domain of thermal-aware testing. Thermal-aware testing can be employed both at circuit level and at system level
Describes range of algorithms for addressing thermal-aware test issue, presents comparison of temperature reduction with power-aware techniques and include results on benchmark circuits and systems for different techniques
This book will be suitable for researchers working on power- and thermal-aware design and the testing of digital VLSI chips
Table of Contents
1.VLSI Testing – An Introduction. 2.Circuit Level Testing. 3. Test Data Compression. 4. System-on-Chip Testing. 5. Network-on-Chip Testing.
Santanu Chattopadhyay received BE degree in Computer Science and Technology from Calcutta University (BE College), Kolkata, India, in 1990. In 1992 and 1996 he received M.Tech in Computer and Information Technology and PhD in Computer Science and Engineering, respectively, both from the Indian Institute of Technology, Kharagpur, India. He is currently a professor in the Electronics and Electrical Communication Engineering department, Indian Institute of Technology, Kharagpur. His research interests include low-power digital circuit design and test, System-on-Chip testing, Network-on-Chip design and test, logic encryption. He has more than hundred publications in refereed international journals and conferences. He is a co-author of the book Additive Cellular Automata – Theory and Applications published by the IEEE Computer Society Press. He has also co-authored the book titled Network-on-Chip The Next Generation of System-on-Chip Integration published by the CRC Press. He has written a number of text books, such as, Compiler Design, System Software, Embedded System Design, all published by the PHI Learning, India. He is a senior member of the IEEE and also one of the regional editors (Asia region) of the IET Circuits, Devices and Systems journal.