Thermal-Aware Testing of Digital VLSI Circuits and Systems: 1st Edition (Hardback) book cover

Thermal-Aware Testing of Digital VLSI Circuits and Systems

1st Edition

By Santanu Chattopadhyay

CRC Press

118 pages | 10 B/W Illus.

Purchasing Options:$ = USD
Hardback: 9780815378822
pub: 2018-04-25
eBook (VitalSource) : 9781351227780
pub: 2018-04-24
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This book aims to highlight the research activities in the domain of thermal-aware testing. Thermal-aware testing can be employed both at circuit level and at system level

Describes range of algorithms for addressing thermal-aware test issue, presents comparison of temperature reduction with power-aware techniques and include results on benchmark circuits and systems for different techniques

This book will be suitable for researchers working on power- and thermal-aware design and the testing of digital VLSI chips

Table of Contents




List of Abbreviations


Chapter 1: VLSI Testing – An Introduction

    1. Testing in VLSI Design Process
    2. Fault Models
    3. Test Generation
    4. Design For Testability
    5. Power Dissipation During Test
    6. Effects of High Temperature
    7. Thermal Model
    8. Summary


Chapter 2: Circuit Level Testing

2.1 Introduction

2.2 Test Vector Reordering

2.3 Don’t Care Filling

2.4 Scan Cell Optimization

2.5 Built-In Self Test

2.6 Summary


Chapter 3: Test Data Compression

3.1 Introduction

3.2 Dictionary Based Test Data Compression

3.3 Dictionary Construction Using Clique Partitioning

3.4 Peak Temperature and Compression Tradeoff

3.5 Temperature Reduction Without Sacrificing Compression

3.6 Summary


Chapter 4: System-on-Chip Testing

4.1 Introduction

4.2 SoC Test Problem

4.3 Superposition Principle Based Thermal Model

4.4 Test Scheduling Strategy

4.5 Experimental Results

4.6 Summary





Chapter 5: Network-on-Chip Testing

5.1 Introduction

5.2 Problem Statement

5.3 Testtime Of NoC

5.4 Peak Temperature Of NoC

5.5 PSO Formulation For Preemptive Test Scheduling

5.6 Augmentation To The Basic PSO

5.7 Overall Algorithm

5.8 Experimental Results

5.9 Summary



About the Author

Santanu Chattopadhyay received BE degree in Computer Science and Technology from Calcutta University (BE College), Kolkata, India, in 1990. In 1992 and 1996 he received M.Tech in Computer and Information Technology and PhD in Computer Science and Engineering, respectively, both from the Indian Institute of Technology, Kharagpur, India. He is currently a professor in the Electronics and Electrical Communication Engineering department, Indian Institute of Technology, Kharagpur. His research interests include low-power digital circuit design and test, System-on-Chip testing, Network-on-Chip design and test, logic encryption. He has more than hundred publications in refereed international journals and conferences. He is a co-author of the book Additive Cellular Automata – Theory and Applications published by the IEEE Computer Society Press. He has also co-authored the book titled Network-on-Chip The Next Generation of System-on-Chip Integration published by the CRC Press. He has written a number of text books, such as, Compiler Design, System Software, Embedded System Design, all published by the PHI Learning, India. He is a senior member of the IEEE and also one of the regional editors (Asia region) of the IET Circuits, Devices and Systems journal.

Subject Categories

BISAC Subject Codes/Headings:
TECHNOLOGY & ENGINEERING / Electronics / General
TECHNOLOGY & ENGINEERING / Electronics / Circuits / General
TECHNOLOGY & ENGINEERING / Electronics / Microelectronics