216 pages | 28 Color Illus. | 108 B/W Illus.
Recent advances in semiconductor technology offer vertical interconnect access (via) that extend through silicon, popularly known as through silicon via (TSV). This book provides a comprehensive review of the theory behind TSVs while covering most recent advancements in materials, models and designs. Furthermore, depending on the geometry and physical configurations, different electrical equivalent models for Cu, carbon nanotube (CNT) and graphene nanoribbon (GNR) based TSVs are presented. Based on the electrical equivalent models the performance comparison among the Cu, CNT and GNR based TSVs are also discussed.
3D Technology and Packaging Techniques. Introduction. Packaging techniques of future ICs. Integrated architectures. Summary. Through Silicon Vias: Materials, Properties and Fabrication. Introduction. History of graphene material. Carbon nanotube. Graphene nanoribbon. Properties of TSV. Fabrication of TSVs. Challenges for the TSV implementations. Summary. Copper Based TSVs. Introduction. Physical configuration. Modelling of Cu based TSVs. Performance analysis of Cu based TSVs. Summary. Carbon Nanotube Based TSVs. Introduction. Physical configuration. Modelling. Performance analysis of CNT based TSVs. Summary. Mixed CNT Bundled Based TSVs. Introduction. Configurations of mixed CNT bundled TSVs. Modelling of MCB based TSVs. Signal integrity analysis of MCB based TSVs. Summary. Graphene Nanoribbon Based TSVs. Introduction. Configurations of GNR based TSVs. Fabrication challenges and limitations. Modelling of GNR based TSVs with smooth edges. Modelling of GNR based TSVs with rough edges. Signal integrity analysis of GNR based TSVs. Summary. Liners in TSVs. Introduction. Types of liners and their impact on performance. Fabrication challenges. Modelling of CNT bundled TSV with SiO2 and polymer liners. Impact of polymer liners on delay. Summary.