Tunneling Field Effect Transistors : Design, Modeling and Applications book cover
1st Edition

Tunneling Field Effect Transistors
Design, Modeling and Applications

  • Available for pre-order on May 11, 2023. Item will ship after June 1, 2023
ISBN 9781032348766
June 1, 2023 Forthcoming by CRC Press
400 Pages 15 Color & 232 B/W Illustrations

FREE Standard Shipping
USD $150.00

Prices & shipping based on shipping country


Book Description

This book will give insight into emerging semiconductor devices from their applications in electronic circuits, which are the backbone of electronic equipment. It provides desired exposure to the ever-growing field of low-power electronic devices and their applications in nanoscale devices, memory design, and biosensing applications.

Tunneling Field Effect Transistors: Design, Modeling, and Applications bring researchers and engineers from various disciplines of the VLSI domain together to tackle the emerging challenges in the field of nanoelectronics and applications of advanced low-power devices. The book begins by discussing the challenges of conventional CMOS technology from the perspective of low-power applications. The book also reviews the basic science and developments of subthreshold swing technology and recent advancements in the field. The authors discuss the impact of semiconductor materials and architecture designs on TFET devices and the performance and usage of FET devices in various domains like nanoelectronics, Memory Devices, and biosensing applications. The authors also cover a variety of FET devices, such as MOSFETs and TFETs, with various structures based on the tunneling transport phenomenon.

The contents of the book have been designed and arranged in such a way that Electrical Engineering students, researchers in the field of nanodevices and device-circuit codesign, as well as industry professionals working in the domain of semiconductor devices, will find the material useful and easy to follow.

Table of Contents

Chapter 1. Challenges of Conventional Cmos Technology in Perspective of Low Power Applications

Chapter 2. Basic Science and Development of Subthreshold Swing Technology

Chapter 3. Historical Development of MOS technology to Tunnel FETs

Chapter 4. Modeling of Gate Engineered TFETs: Challenges and Opportunities

Chapter 5. Modeling of Gate Engineered TFET: challenges and Opportunities.

Chapter 6. Evolution of Heterojunction Tunnel Field Effect Transistor and its Advantages

Chapter 7. Analog / RF performance analysis of TFET device

Chapter 8. DC Analysis and Analog/HF Performances of GAA-TFET with Dielectric Pocket

Chapter 9. Investigation on Ambipolar Current Suppression in Tunnel FETs

Chapter 10. Analysis of Channel Doping Variation on Transfer Characteristics to High Frequency performance of F-TFET

Chapter 11. Design of Nanotube TFET Biosensor

Chapter 12. TFET-based Memory Cell Design with Top-down Approach

Chapter 13. Designing of nonvolatile memories utilizing Tunnel Field Effect Transistor

Chapter 14. TFET-based Universal

Chapter 15. TFET-based Level Shifter Circuits for Low Power Applications

View More



Arun Samuel T.S received a B.E degree in Electronics and Communication Engineering from Syed Ammal Engineering College (2004) and M.E degree in Computer and communication engineering from the National Engineering College (2006). He has been awarded a Ph.D. in Nanoelectronic Devices (2014) from Thiagarajar College of Engineering, Tamilnadu, India, under Anna University Chennai. He is currently an Associate Professor at the National Engineering College, Kovilpatti, India. He is a lifetime member of the Institute of Engineering (IE), India, and a member of IEEE. His research interest includes Modelling and Simulation of Multigate transistors and Tunnel Field-effect Transistors.

Professor Young Suh Song is an Assistant Professor in the Department of Computer Science (CS) at the Korea Military Academy. His current research interests have included semiconductor reliability (self-heating effect and retention characteristics), AI semiconductor, Machine Learning (ML) for demographics and economics, NAND Flash and NOR Flash, low-temperature logic device for CPU, low power logic device (Tunnel FET, TFET) for cell phone and laptop, and germanium (Ge) based logic device (2030 ~ 2050) which is one of the promising candidates for replacing current silicon (Si) based CPU technology.

Dr. Shubham Tayal is an Assistant Professor in the Department of Electronics and Communication Engineering at SR University, Warangal, India. He has more than 6 Years of academic/research experience teaching at the UG and PG levels. He has received his Ph.D. in Microelectronics & VLSI Design from the National Institute of Technology, Kurukshetra, M.Tech (VLSI Design) from YMCA University of Science and Technology, Faridabad, and B.Tech (Electronics and Communication Engineering) from MDU, Rohtak. He is a recipient of the Green ThinkerZ International Distinguished Young Researcher Award 2020. His research interests include simulation and modeling of Multi-gate semiconductor devices, Device-Circuit co-design in digital/analog domain, machine learning, and IoT.

P.Vimala received her B.E and M.E degrees, both in electronics and communication engineering from Anna University, Chennai. She completed her Ph.D. degree in Semiconductor device modeling and simulation at Anna University, Chennai in 2014. She is currently an Associate Professor at Dayananda Sagar College of Engineering, Bangalore, India. She has 100+ publications including 47 indexed journals and 30+ indexed conferences, 1 patent, and 5 book chapters. She is a Senior Member of IEEE, a Fellow of IETE, a Life Member of ISTE, and a member of IEI. Her research interests focused on the Modeling of Nanoscale semiconductor device modeling and Simulation using both Sentaurus and Atlas TCAD Simulation tool.

Shiromani Balmukund Rahi received B.Sc. (Physics, Chemistry & Mathematics) in 2002, M.Sc. (Electronics) from Deen Dyal Upadhyaya Gorakhpur University, Gorakhpur in 2005, GATE (2009), M. Tech. (Microelectronics) from Panjab University Chandigarh in 2011 and Doctorate of Philosophy in 2018 from Indian Institute of Technology, Kanpur, India. His interests include the development of IoTs for smart applications for the development of ultra-low-power devices such as Tunnel FETs, NC TFET Negative Capacitance FETs, Nanosheet.