BiographyDr. Angsuman Sarkar is presently serving as an Associate Professor of Electronics and Communication Engineering in Kalyani Government Engineering College, West Bengal. He had earlier served Jalpaiguri Government Engineering College, West Bengal as a Lecturer of ECE department for 10 years. He received the M.Tech degree in VLSI & Microelectronics from Jadavpur University. He completed his Ph.D from Jadavpur University in 2013. His current research interest span around study of short channel effects of sub 100nm MOSFETs and nano device modeling. He is a a Senior Member of IEEE, Life Member of Indian Society for Technical Education (ISTE), Associate Life Member of Institution of Engineers (IE) India and currently serving as the Chairman of IEEE Electron Device Society, Kolkata Chapter. He has authored 5 books, 3 contributed book chapters, 54 journal papers in international refereed journals and 24 research papers in national and international conferences. He is a member of board of editors of various journals. He is reviewer of various international journals. He is currently supervising 6 Ph.D. scholars. He has delivered invited talk/tutorial speech/expert talk in various International Conference /technical programs. He has organized IEEE international conferences and several workshops/seminars.
Areas of Research / Professional Expertise
As device scaling continues to sub-100nm regime, it is become crucial to identify the detrimental short-channel effects and their remedies. Therefore, the study of short-channel effects and their remedies is a principal problem of great magnitude in the perspective of integrated circuit (IC) manufacturing and related reliability issues.The research interest of Dr. Sarkar spans around the study, discussion and investigation of the effect of diminishing MOS channel length on device characterizes and their remedies by novel unconventional device structures, highlighting his concept of MOSFET device physics and knowledge of scaling trends in MOSFET evolution using device modeling and TCAD simulation.It is also equally important to identify the analog/RF characteristics of the novel device structures, envisioned as a future replacement of silicon planar MOSFETs in digital circuits and is a potential candidate for providing long-term solutions to continue scaling CMOS beyond the 100-nm technology node, in order to use them in in a mixed-signal System-on-Chip (SoC) applications.
MOS Device Physics
Scaling of MOSFET
Nano-scale MOSFET Modelling & Simulation
TCAD device Simulation (Silvaco)
RF/Analog Performance investigation of novel MOS device structures
Classification of single and double-gate nanoscale MOSFET with different dielectrics from electrical characteristics using soft computing techniques
Published: Apr 05, 2019 by International Journal of Information Technology
Authors: A. Deyasi, S. Mukherjee, A. K. Bhattacharjee and A. Sarkar
Subjects: Engineering - Electrical
Near-accurate classification is possible for single and double-gate nano-MOSFETs with low and high-k dielectrics based on the experimental findings of their electrical performance.