Advanced VLSI Design and Testability Issues  book cover
1st Edition

Advanced VLSI Design and Testability Issues

  • Available for pre-order. Item will ship after April 15, 2022
ISBN 9780367538361
April 15, 2022 Forthcoming by CRC Press
378 Pages 192 B/W Illustrations

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Book Description

This book facilitates the VLSI-interested individuals with not only in-depth knowledge, but also the broad aspects of it by explaining its applications in different fields, including image processing and biomedical. The deep understanding of basic concepts gives you the power to develop a new application aspect, which is very well taken care of in this book by using simple language in explaining the concepts. In the VLSI world, the importance of hardware description languages cannot be ignored, as the designing of such dense and complex circuits is not possible without them. Both Verilog and VHDL languages are used here for designing. The current needs of high-performance integrated circuits (ICs) including low power devices and new emerging materials, which can play a very important role in achieving new functionalities, are the most interesting part of the book. The testing of VLSI circuits becomes more crucial than the designing of the circuits in this nanometer technology era. The role of fault simulation algorithms is very well explained, and its implementation using Verilog is the key aspect of this book.

This book is well organized into 20 chapters. Chapter 1 emphasizes on uses of FPGA on various image processing and biomedical applications. Then, the descriptions enlighten the basic understanding of digital design from the perspective of HDL in Chapters 2–5. The performance enhancement with alternate material or geometry for silicon-based FET designs is focused in Chapters 6 and 7. Chapters 8 and 9 describe the study of bimolecular interactions with biosensing FETs. Chapters 10–13 deal with advanced FET structures available in various shapes, materials such as nanowire, HFET, and their comparison in terms of device performance metrics calculation. Chapters 14–18 describe different application-specific VLSI design techniques and challenges for analog and digital circuit designs. Chapter 19 explains the VLSI testability issues with the description of simulation and its categorization into logic and fault simulation for test pattern generation using Verilog HDL. Chapter 20 deals with a secured VLSI design with hardware obfuscation by hiding the IC’s structure and function, which makes it much more difficult to reverse engineer.

Table of Contents

Chapter 1 Digital Design with Programmable Logic Devices

M. Panigrahy, S. Jena, and R. L. Pradhan

Chapter 2 Review of Digital Electronics Design

Reena Chandel, Dushyant Kumar Singh, and P. Raja

Chapter 3 Verilog HDL for Digital and Analog Design

Ananya Dastidar

Chapter 4 Introduction to Hardware Description Languages

Shasanka Sekhar Rout and Salony Mahapatro

Chapter 5 Introduction to Hardware Description Languages (HDLs)

P. Raja, Dushyant Kumar Singh, and Himani Jerath

Chapter 6 Emerging Trends in Nanoscale Semiconductor Devices

B. Vandana, B. S. Patro, J. K. Das, S. K. Mohapatra, and Suman Lata Tripathi

Chapter 7 Design Challenges and Solutions in CMOS-Based FET

Madhusmita Mishra and Abhishek Kumar

Chapter 8 Analytical Design of FET-Based Biosensors

Khuraijam Nelson Singh and Pranab Kishore Dutta

Chapter 9 Low-Power FET-Based Biosensors

Prasantha R. Mudimela and Rekha Chaudhary

Chapter 10 Nanowire Array–Based Gate-All-Around MOSFET for Next-Generation Memory Devices

Krutideepa Bhol, Biswajit Jena, and Umakanta Nanda

Chapter 11 Design of 7T SRAM Cell Using FinFET Technology

T. Santosh Kumar and Suman Lata Tripathi

Chapter 12 Performance Analysis of AlGaN/GaN Heterostructure Field-Effect Transistor (HFET)

Yogesh Kumar Verma and Santosh Kumar Gupta

Chapter 13 Synthesis of Polymer-Based Composites for Application in Field-Effect Transistors

Amit Sachdeva and Pramod K. Singh

Chapter 14 Power Efficiency Analysis of Low-Power Circuit Design Techniques in 90-nm CMOS Technology

Yelithoti Sravana Kumar, Tapaswini Samant, and Swati Swayamsiddha

Chapter 15 Macromodeling and Synthesis of Analog Circuits

B. S. Patro and Sushanta Kumar Mandal

Chapter 16 Performance-Linked Phase-Locked Loop Architectures: Recent Developments

Umakanta Nanda, Debiprasad Priyabrata Acharya, Prakash

Kumar Rout, Debasish Nayak, and Biswajit Jena

Chapter 17 Review of Analog-to-Digital and Digital-to-Analog Converters for A Smart Antenna Application

B. S. Patro, A. Senapati, and T. Pradhan

Chapter 18 Active Inductor–Based VCO for Wireless Communication

Aditya Kumar Hota, Shasanka Sekhar Rout, and Kabiraj Sethi

Chapter 19 Fault Simulation Algorithms: Verilog Implementation

Sobhit Saxena

Chapter 20 Hardware Protection through Logic Obfuscation

Jyotirmoy Pathak and Suman Lata Tripathi


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Suman Lata Tripathi is associated with Lovely Professional University, Phagwara, Punjab, as Professor with more than seventeen years of experience in academics. Her area of expertise includes microelectronics device modeling and characterization, low power VLSI circuit design, VLSI design of testing and advance FET design for IOT and biomedical applications etc. Sobhit Saxena is an Associate Professor at Lovely Professional University University, Phagwara, Punjab. His area of expertise includes nanomaterial synthesis and characterization, electrochemical analysis and modeling and simulation of CNT based interconnects for VLSI circuits. S. K. Mohapatra is working as Assistant Professor, in School of Electronics Engineering, Kalinga Institute of Industrial Technology, Bhubaneswar. His research interests include Modeling and Simulation of Nanoscale Devices and its application in IoT. Energy efficient Wireless Sensor Networking, Adhoc Networks, Cellular Communications, Metamaterial absorbers in THz application, UWB-MIMO Antenna, Reconfigurable Antenna, Performance enhancement for high frequency.