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Bio-Inspired Fault-Tolerant Algorithms for Network-on-Chip




ISBN 9780367425906
Published April 7, 2020 by CRC Press
212 Pages 66 B/W Illustrations

 
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Book Description

Network on Chip (NoC) addresses the communication requirement of different nodes on System on Chip. The bio-inspired algorithms improve the bandwidth utilization, maximize the throughput and reduce the end-to-end latency and inter-flit arrival time. This book exclusively presents in-depth information regarding bio-inspired algorithms solving real world problems focussing on fault-tolerant algorithms inspired by the biological brain and implemented on NoC. It further documents the bio-inspired algorithms in general and more specifically, in the design of NoC. It gives an exhaustive review and analysis of the NoC architectures developed during the last decade according to various parameters.

Key Features:

  • Covers bio-inspired solutions pertaining to Network-on-Chip (NoC) design solving real world examples
  • Includes bio-inspired NoC fault-tolerant algorithms with detail coding examples
  • Lists fault-tolerant algorithms with detailed examples
  • Reviews basic concepts of NoC
  • Discusses NoC architectures developed-to-date

Table of Contents

Chapter 1: (Introduction)

1.1 Network on Chip

1.2 Fault tolerance

1.3 Why Bio-inspired Algorithms For Fault tolerance

1.4 Bio-inspired Fault-tolerant Algorithms Objectives

1.5 Book Contributions

1.6 Organization of the Book

Chapter 2: (In-depth Review of Network on Chip)

2.1 Link Sharing Mechanism

2.3 Switching Techniques

2.4 Buffer Management Techniques

2.5 NoC Evaluation Parameters

2.6 NoC Clocking Mechanism

2.7 NoC Topologies

2.8 Open Source

2.9 NoC Connection Types

2.10 NoC Size

2.11 NoC Implementation Platforms

2.12 NoC Buffering Mechanisms

2.13 NoC PE-router Interface

2.14 NoC Frequency and Technology

2.15 NoC Area and Power Consumption

2.16 NoC Router Ports and Bus Width

2.17 NoC Year of Proposal, Flit size and Latency

2.18 Quality of Services (QoS)

Summary

Chapter 3: (Bio-inspired algorithms and implementation)

3.1 Swarm Intelligence Algorithms (SIA)

3.2 Ant Colony Optimization (ACO)

3.3 Artificial Immune System (AIS)

3.4 Firefly Algorithm

3.5 Epidemic Spreading

3.6 Flower Pollination Algorithm (FPA)

3.7 Artificial Bee Colony Algorithm (ABC)

3.8 Cat Swarm Optimization (CSO)

3.9 Cuckoo Search (CS)

3.10 Bat Algorithm (BA)

3.11 Cuttlefish Algorithm (CFA)

3.12 Harris Hawks Optimization (HHO)

3.13 Killer Whale Algorithm (KWA)

3.14 Cobweb Network on Chip (NoC) Topology

3.15 Scalable Bio-inspired Fault Detection Unit (FDU) in Network on Chip

3.16 Autonomous Error Tolerant (AET) Architecture

3.17 SpiNNaker Communication

3.18 Autonomic Network on Chip using the Biological Immune System

3.19 Fault-Tolerant NoC using Biological Brain Techniques

3.20 Bio-Inspired Online Fault Detection in NoC Interconnect

3.21 Bio-inspired Self-Aware NoC Fault-Tolerant Routing Algorithm

Chapter 4: (Bio-inspired NoC fault-tolerant algorithms)

4.1 Biological Brain Characteristics

4.2 Synaptogenesis

4.3 Sprouting

4.4 Bio-inspired NoC Algorithms

4.5 Bio-inspired NoC Framework

4.6 Bio-inspired NoC Network

4.7 Bio-inspired NoC Fault-Tolerant Algorithm

4.8 Bio-inspired BE and GT NoC algorithm and architectures

Summary

Chapter 5: (Analysis of bio-inspired NoC fault-tolerant algorithms)

5.1 Research framework, design and parameters

5.2 Bio-inspired NoC fault-tolerant algorithms result analysis

Summary

Chapter 6: (Conclusion and future work)

6.1 Future work

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Author(s)

Biography

Dr. Muhammad Athar Javed Sethi is an Assistant Professor at the Department of Computer Systems Engineering, University of Engineering and Technology (UET), Peshawar, Pakistan. He received the Bachelor of Sciences in Computer Information Systems Engineering (honors) from the UET Peshawar, Pakistan in 2004. He had done Master of Sciences in Computer Systems Engineering from the same university in 2008. He completed his Ph.D. at Universiti Teknologi PETRONAS (UTP), Malaysia in Department of Electrical & Electronic Engineering in 2016. He was able to get different scholarships to pursue and continue his studies. Dr. Sethi got IEEE student best paper award in the year 2013 and a most downloaded paper award from Elsevier in consecutive two years 2016-2017 for two different papers. His research interests include network on chip (NoC), interconnection networks, computer architecture, and embedded systems. Dr. Sethi, has published numerous manuscripts in reputable Journals, Conferences and Books. Currently, he is also actively involved in technical program committees of various international conferences. He is serving as Associate Editor at EAI Endorsed Transactions on Context-aware Systems & Applications and at EAI Endorsed Transactions on Ambient Systems.