Computer Arithmetic and Verilog HDL Fundamentals

Description

Verilog Hardware Description Language (HDL) is the state-of-the-art method for designing digital and computer systems. Ideally suited to describe both combinational and clocked sequential arithmetic circuits, Verilog facilitates a clear relationship between the language syntax and the physical hardware. It provides a very easy-to-learn and practical means to model a digital system at many levels... Read more

Verilog Hardware Description Language (HDL) is the state-of-the-art method for designing digital and computer systems. Ideally suited to describe both combinational and clocked sequential arithmetic circuits, Verilog facilitates a clear relationship between the language syntax and the physical hardware. It provides a very easy-to-learn and practical means to model a digital system at many levels of abstraction.

Computer Arithmetic and Verilog HDL Fundamentals details the steps needed to master computer arithmetic for fixed-point, decimal, and floating-point number representations for all primary operations. Silvaco International’s SILOS, the Verilog simulator used in these pages, is simple to understand, yet powerful enough for any application. It encourages users to quickly prototype and de-bug any logic function and enables single-stepping through the Verilog source code. It also presents drag-and-drop abilities.

Introducing the three main modeling methods—dataflow, behavioral, and structural—this self-contained tutorial—

Covers the number systems of different radices, such as octal, decimal, hexadecimal, and binary-coded variations

Reviews logic design fundamentals, including Boolean algebra and minimization techniques for switching functions

Presents basic methods for fixed-point addition, subtraction, multiplication, and division, including the use of decimals in all four operations

Addresses floating-point addition and subtraction with several numerical examples and flowcharts that graphically illustrate steps required for true addition and subtraction for floating-point operands

Demonstrates floating-point division, including the generation of a zero-biased exponent

Designed for electrical and computer engineers and computer scientists, this book leaves nothing unfinished, carrying design examples through to completion. The goal is practical proficiency. To this end, each chapter includes problems of varying complexity to be designed by the reader.

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Author(s)

Biography

Joseph Cavanagh is an adjunct professor in the computer engineering department at Santa Clara University in California.

Critics' Reviews

"Cavanagh has provided readers with a very large work on the topics of addition, subtraction, multiplication, and division. … The student who completes a course based on this work will have achieved a great deal. Summing Up: Recommended."
—CHOICE, June 2010

Computer Arithmetic and Verilog HDL Fundamentals

Description

Table of Contents

Author(s)

Biography

Critics' Reviews

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