Design Rules in a Semiconductor Foundry  book cover
1st Edition

Design Rules in a Semiconductor Foundry

Edited By

Eitan N. Shauly

ISBN 9789814968003
Published November 30, 2022 by Jenny Stanford Publishing
830 Pages 154 Color & 248 B/W Illustrations

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Book Description

Nowadays over 50% of integrated circuits are fabricated at wafer foundries. This book presents a foundry-integrated perspective of the field and is a comprehensive and up-to-date manual designed to serve process, device, layout, and design engineers. It comprises chapters carefully selected to cover topics relevant for them to deal with their work. The book provides an insight into the different types of design rules (DRs) and considerations for setting new DRs. It discusses isolation, gate patterning, S/D contacts, metal lines, MOL, air gaps, and so on. It explains in detail the layout rules needed to support advanced planarization processes, different types of dummies, and related utilities as well as presents a large set of guidelines and layout-aware modeling for RF CMOS and analog modules. It also discusses the layout DRs for different mobility enhancement techniques and their related modeling, listing many of the dedicated rules for static random-access memory (SRAM), embedded polyfuse (ePF), and LogicNVM. The book also provides the setting and calibration of the process parameters set and describes the 28~20 nm planar MOSFET process flow for low-power and high-performance mobile applications in a step-by-step manner. It includes FEOL and BEOL physical and environmental tests for qualifications together with automotive qualification and design for automotive (DfA). Written for the professionals, the book belongs to the bookshelf of microelectronic discipline experts.

Table of Contents

1. Layout Design Rules: Definition, Setting and Scaling 
Eitan N. Shauly 
2. Front-End-Of-Line Topological Design Rules 
Eitan N. Shauly 
3. Back-End-Of-Line Topological Design Rules 
Eitan N. Shauly 
4. Coverage Rules and Insertion Utilities 
Eitan N. Shauly 
5. Design Rules, Guidelines, and Modeling for Analog Modules 
Samir Chaudhry and Eitan N. Shauly 
6. Stress-Related Layout Design Rules and Modeling 
Eitan N. Shauly 
7. Dedicated Design Rules for Memory Modules 
Yakov Roizin, Evgeny Pikhay, and Eitan N. Shauly 
8. Planar CMOS Process Flow for Digital, Mixed-Signal and RFCMOS Applications 
Eitan N. Shauly 
9. Reliability Driven Design Rules 
Kenji Okada and Eitan N. Shauly 

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Eitan N. Shauly is the director of integration at Tower Semiconductor Ltd., Israel, since 1998. He has been with the organization since 1989, initially as a diffusion and ion implantation engineer and a device/integration engineer and later focusing on process integration, modeling, and design rules as well as incorporating new technology in the company’s foundries. Dr Shauly also teaches courses related to VLSI technology in the Faculty of Materials Science and Engineering, Technion – Israel Institute of Technology, Haifa, Israel. He received his BSc (1989) in materials engineering from Ben-Gurion University, Beer-Sheva, Israel, and MSc (1995) and PhD (2001) in materials engineering from the Technion – Israel Institute of Technology.