1. Layout Design Rules: Definition, Setting and Scaling
Eitan N. Shauly
2. Front-End-Of-Line Topological Design Rules
Eitan N. Shauly
3. Back-End-Of-Line Topological Design Rules
Eitan N. Shauly
4. Coverage Rules and Insertion Utilities
Eitan N. Shauly
5. Design Rules, Guidelines, and Modeling for Analog Modules
Samir Chaudhry and Eitan N. Shauly
6. Stress-Related Layout Design Rules and Modeling
Eitan N. Shauly
7. Dedicated Design Rules for Memory Modules
Yakov Roizin, Evgeny Pikhay, and Eitan N. Shauly
8. Planar CMOS Process Flow for Digital, Mixed-Signal and RFCMOS Applications
Eitan N. Shauly
9. Reliability Driven Design Rules
Kenji Okada and Eitan N. Shauly
Biography
Eitan N. Shauly is the director of integration at Tower Semiconductor Ltd., Israel, since 1998. He has been with the organization since 1989, initially as a diffusion and ion implantation engineer and a device/integration engineer and later focusing on process integration, modeling, and design rules as well as incorporating new technology in the company’s foundries. Dr Shauly also teaches courses related to VLSI technology in the Faculty of Materials Science and Engineering, Technion – Israel Institute of Technology, Haifa, Israel. He received his BSc (1989) in materials engineering from Ben-Gurion University, Beer-Sheva, Israel, and MSc (1995) and PhD (2001) in materials engineering from the Technion – Israel Institute of Technology.
