3D Integration Technology with TSV and IMC Bonding. Wafer-Level 3D ICs for Advanced CMOS Integration. Integration of Graphics Processing Cores with Microprocessors. Electrothermal Simulation of 3D ICs. Thermal Management in 3D ICs/Systems. Emerging Interconnect Technologies for 3D Networks-on-Chips. Inductive-Coupling ThruChip Interface for 3D Integration. Fabrication and Modeling of Copper and Carbon Nanotube-Based Through-Silicon Via. Low-Power Testing for 2D/3D Devices and Systems.
Biography
Rohit Sharma is faculty at the Indian Institute of Technology Ropar, Punjab. He previously worked as a post-doctoral researcher at Seoul National University, South Korea and at Georgia Institute of Technology, Atlanta, USA. Dr. Sharma has authored/co-authored over 50 journal and conference publications, one book, one book chapter, two patents/copyrights, and several invited talks. He was a recipient of the Brain Korea Research Fellowship (2010), the Indo-US Research Fellowship (2011), and Best Paper Awards in ASQED 2010 and GIT 2011 conferences. An IEEE and ACM member, he has served as a journal referee and committee member/session co-chair on multiple occasions.
