Three-dimensional (3D) integration of microsystems and subsystems has become essential to the future of semiconductor technology development. 3D integration requires a greater understanding of several interconnected systems stacked over each other. While this vertical growth profoundly increases the system functionality, it also exponentially increases the design complexity.
Design of 3D Integrated Circuits and Systems tackles all aspects of 3D integration, including 3D circuit and system design, new processes and simulation techniques, alternative communication schemes for 3D circuits and systems, application of novel materials for 3D systems, and the thermal challenges to restrict power dissipation and improve performance of 3D systems. Containing contributions from experts in industry as well as academia, this authoritative text:
- Illustrates different 3D integration approaches, such as die-to-die, die-to-wafer, and wafer-to-wafer
- Discusses the use of interposer technology and the role of Through-Silicon Vias (TSVs)
- Presents the latest improvements in three major fields of thermal management for multiprocessor systems-on-chip (MPSoCs)
- Explores ThruChip Interface (TCI), NAND flash memory stacking, and emerging applications
- Describes large-scale integration testing and state-of-the-art low-power testing solutions
Complete with experimental results of chip-level 3D integration schemes tested at IBM and case studies on advanced complementary metal–oxide–semiconductor (CMOS) integration for 3D integrated circuits (ICs), Design of 3D Integrated Circuits and Systems is a practical reference that not only covers a wealth of design issues encountered in 3D integration but also demonstrates their impact on the efficiency of 3D systems.
Table of Contents
3D Integration Technology with TSV and IMC Bonding. Wafer-Level 3D ICs for Advanced CMOS Integration. Integration of Graphics Processing Cores with Microprocessors. Electrothermal Simulation of 3D ICs. Thermal Management in 3D ICs/Systems. Emerging Interconnect Technologies for 3D Networks-on-Chips. Inductive-Coupling ThruChip Interface for 3D Integration. Fabrication and Modeling of Copper and Carbon Nanotube-Based Through-Silicon Via. Low-Power Testing for 2D/3D Devices and Systems.
Rohit Sharma is faculty at the Indian Institute of Technology Ropar, Punjab. He previously worked as a post-doctoral researcher at Seoul National University, South Korea and at Georgia Institute of Technology, Atlanta, USA. Dr. Sharma has authored/co-authored over 50 journal and conference publications, one book, one book chapter, two patents/copyrights, and several invited talks. He was a recipient of the Brain Korea Research Fellowship (2010), the Indo-US Research Fellowship (2011), and Best Paper Awards in ASQED 2010 and GIT 2011 conferences. An IEEE and ACM member, he has served as a journal referee and committee member/session co-chair on multiple occasions.