1st Edition
Design of Cost-Efficient Interconnect Processing Units Spidergon STNoC
Towards Multicores: Technology and Software Complexity
Multicore Architecture, Algorithms and Applications
Complexity in Embedded Software
Technological Issues in Multicore Architectures
On-Chip Bus vs Network-on-Chip
Transition from On-Chip Bus to Network-on-Chip
Popular SoC Buses
Existing NoC Architectures
NoC Topology
On-chip Network topology
Multistage Interconnection Networks
Mesh and Torus
Chordal Rings
Other Constant Degree Topologies
The Spidergon STNoC Topology
Comparisons based on Topology Metrics
The Spidergon STNoC
Spidergon STNoC Interconnect Processing Unit
Switching Strategy
Communication Layering and Packet Structure
Routing Algorithms
Livelock, Starvation, and Deadlock
Protocol Deadlock Avoidance in Spidergon STNoC
Spidergon STNoC Building Blocks
Tile-based Architecture
SoC and NoC Design Methodology and Tools
SoC Design Methodology and Tools
NoC Design Methodology and Tools
The On-Chip Communication Network (OCCN)
Conclusions and Future Work
Enhanced IPU Programmability Portfolio
IPU Physical Design
IPU Design Tools
IPU Design and Verification Methodology
Biography
Marcello Coppola (STMicroelectronics, Grenoble, France) (Author) , Miltos D. Grammatikakis (ISD SA, Heraklion, Greece) (Author) , Riccardo Locatelli (STMicroelectronics, Grenoble Cedex, France) (Author) , Giuseppe Maruccia (STMicroelectronics, Grenoble, France) (Author) , Lorenzo Pieralisi (STMicroelectronics, Grenoble, France) (Author)
