1st Edition
Digital Integrated Circuits Design-for-Test Using Simulink and Stateflow
By Evgeni Perelroyzen
Copyright 2007
320 Pages
402 B/W Illustrations
by
CRC Press
320 Pages
402 B/W Illustrations
by
CRC Press
Also available as eBook on:
A current trend in digital design-the integration of the MATLAB® components Simulink® and Stateflow® for model building, simulations, system testing, and fault detection-allows for better control over the design flow process and, ultimately, for better system results. Digital Integrated Circuits: Design-for-Test Using Simulink® and Stateflow® illustrates the construction of Simulink models for... Read more
INTRODUCTION
SIMULINK®: DYNAMIC SYSTEM SIMULATION FOR MATLAB®
Introduction
Creating a Model
Running a Simulation
Analyzing Simulation Results
Subsystems: Using Masks to Customize Blocks
Reference Blocks
Simulink Debugger
STATEFLOW®: CREATING FINITE STATE MACHINE MODELS
Introduction
Creating Charts
Entering a Stateflow Diagram
Defining Events and Data
Defining Stateflow Interfaces
Exploring and Searching
Debugging
FAULT MODELING AND SIMULATION
Fault Modeling
Fault Simulation
TESTABILITY ANALYSIS METHODS
Combinational Controllability and Observability Analysis Models
Sequential Controllability and Observability Analysis Models
THE AUTOMATIC TEST PATTERN GENERATION (ATPG) PROCESS
ATPG Fundamentals
Combinational Circuit ATPG (Current-Based ATPG Algorithms for Combinational Circuits)
TIMING VERIFICATION
Logical Determinant Theory
Digital Circuit Dynamics
Model Building for Timing Verification
SYSTEM AND EMBEDDED CORE TESTING
Introduction
Scan Path Architectures and Techniques
System and Embedded Core Testing
INDEX
References appear at the end of each chapter.
SIMULINK®: DYNAMIC SYSTEM SIMULATION FOR MATLAB®
Introduction
Creating a Model
Running a Simulation
Analyzing Simulation Results
Subsystems: Using Masks to Customize Blocks
Reference Blocks
Simulink Debugger
STATEFLOW®: CREATING FINITE STATE MACHINE MODELS
Introduction
Creating Charts
Entering a Stateflow Diagram
Defining Events and Data
Defining Stateflow Interfaces
Exploring and Searching
Debugging
FAULT MODELING AND SIMULATION
Fault Modeling
Fault Simulation
TESTABILITY ANALYSIS METHODS
Combinational Controllability and Observability Analysis Models
Sequential Controllability and Observability Analysis Models
THE AUTOMATIC TEST PATTERN GENERATION (ATPG) PROCESS
ATPG Fundamentals
Combinational Circuit ATPG (Current-Based ATPG Algorithms for Combinational Circuits)
TIMING VERIFICATION
Logical Determinant Theory
Digital Circuit Dynamics
Model Building for Timing Verification
SYSTEM AND EMBEDDED CORE TESTING
Introduction
Scan Path Architectures and Techniques
System and Embedded Core Testing
INDEX
References appear at the end of each chapter.
Biography
Evgeni Perelroyzen
