3rd Edition
Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology Volume 2
Section I — RTL to GDS‑II , or Synthesis, Place, and Route
Chapter 1 Design Flows
David Chinnery, Piyush Verma, Leon Stok, David Hathaway, and Kurt Keutzer
Chapter 2 Logic Synthesis
Ankush Sood, Taher Abbasi, Adel Khouja, Jean‑Charles Giomi, Sunil Khatri, and Narendra Shenoy
Chapter 3 Power Analysis and Optimization from Circuit to Register Transfer Levels
José Monteiro, Rakesh Patel, and Vivek Tiwari
Chapter 4 Equivalence Checking
Andreas Kuehlmann, Fabio Somenzi, Chih‑Jen Hsu, and Doron Bustan
Chapter 5 Digital Layout Placement
Andrew B. Kahng and Sherief Reda
Vidya A. Chhabria, Jordi Cortadella, and Sachin S. Sapatnekar
Chapter 7 Structured Digital Design
Minsik Cho, Mihir Choudhury, Ruchir Puri, Haoxing Ren, Hua Xiang, Gi‑Joon Nam, Fan Mo, and Robert K. Brayton
Chapter 8 Routing
Gustavo E. Téllez, Jin Hu, and Yaoguang Wei
Chapter 9 Physical Design for 3D ICs
Sung‑Kyu Lim
Chapter 10 Gate Sizing
Stephan Held and Jiang Hu
Chapter 11 Clock Design and Synthesis
Matthew R. Guthaus
Chapter 12 Exploring Challenges of Libraries for Electronic Design
James Hogan, Scott T. Becker, and Neal Carney
Chapter 13 Design Closure
Peter J. Osler, John M. Cohn, and David Chinnery
Chapter 14 Tools for Chip‑Package Codesign
Paul D. Franzon and Madhavan Swaminathan
Chapter 15 Design Databases
Mark Bales
Chapter 16 FPGA Synthesis and Physical Design
Jason Anderson, Vaughn Betz, and Mike Hutton
Section II — Analog and Mixed‑Signal Design
Chapter 17 Simulation of Analog and RF Circuits and Systems
Jaijeet Roychowdhury and Alan Mantooth
Chapter 18 Simulation and Modeling for Analog and Mixed‑Signal Integrated Circuits
Georges G.E. Gielen and Joel R. Phillips
John M. Cohn, Ramesh Harjani, Mark Po‑Hung Lin, Rob A. Rutenbar, and Sachin S. Sapatnekar
Section III — Physical Verification
Chapter 20 Design Rule Checking
Robert Todd, Laurence Grodd, Jimmy Tomblin, Katherine Fetty, and Daniel Liddell
Chapter 21 Resolution Enhancement Techniques and Mask Data Preparation
Franklin M. Schellenberg
Nicola Dragone, Carlo Guardiani, and Andrzej J. Strojwas
Chapter 23 Design and Analysis of Power Supply Networks
Rajendran Panda, Sanjay Pant, David Blaauw, and Rajat Chaudhry
Chapter 24 Noise in Digital ICs
Ashish Sharma and Ioannis Savidis
Chapter 25 Layout Extraction
William Kao, Chi‑Yuan Lo, Mark Basel, Raminderpa Singh, Peter Spink, and Louis K. Scheffer
Chapter 26 Mixed‑Signal Noise Coupling in System‑on‑Chip Design: Modeling, Analysis, and Validation
Nishath Verghese and Nagata Makoto
Section IV — Technology Computer‑Aided Design
Chapter 27 Process Simulation
Mark D. Johnson
Robert W. Dutton, Chang‑Hoon Choi, and Edwin C. Kan
Chapter 29 High‑Accuracy Parasitic Extraction
Zhengfeng (Jeff) Wu and Ioannis Savidis
Biography
Luciano Lavagno received his Ph.D. in EECS from U.C. Berkeley in 1992 and from Politecnico di Torino in 1993. He co-authored two books on asynchronous circuit design, a book on hardware/software co-design of embedded systems, and over 250 scientific papers. Between 1993 and 2000 he was the architect of the POLIS project, a cooperation between U.C. Berkeley, Cadence Design Systems, Magneti Marelli and Politecnico di Torino, which developed a complete hardware/software co-design environment for control-dominated embedded systems. Between 2003 and 2014 he was one of the creators and architects of the Cadence CtoSilicon high-level synthesis system. Since 2011, Dr. Lavagno has been a full professor with Politecnico di Torino, Italy. He has served on the technical committees of several international conferences in his field (e.g. DAC, DATE, ICCAD, ICCD, ASYNC, CODES) as well as various workshops and symposia and is a senior member of IEEE. He has also been an associate editor of IEEE TCAS and ACM TECS. His research interests include the high-level synthesis of digital circuits and the acceleration of Machine learning algorithms using Field Programmable Gate Arrays.
Grant E. Martin retired from his position as a distinguished engineer at Cadence Design Systems, Inc., San Jose, California, USA, in 2023. Before that, Grant worked for Burroughs in Scotland for 6 years; Nortel/Bell-Northern Research in Canada for 10 years; Cadence Design Systems for 9 years, eventually becoming a fellow in their labs; and Tensilica for 9 years. He rejoined Cadence in 2013 when it acquired Tensilica, and has been there since, working in the Tensilica part of the Cadence Intellectual Property Group. He received his bachelor’s and master’s degrees in mathematics (combinatorics and optimization) from the University of Waterloo, Ontario, Canada, in 1977 and 1978. Grant has coauthored and coedited several books, including the first-ever book on system-on-chip (SoC) design published in Russian. He has also presented many papers, talks, and tutorials, and participated in panels at several major conferences. He cochaired the VSI Alliance Embedded Systems Study Group in the summer of 2001 and was co-chair of the Design Automation Conference Technical Program Committee for Methods for 2005 and 2006. He is a senior member of IEEE. Although retired, he continues to have an interest in system-level design, IP-based design of system-on-chip, platform-based design, DSP, baseband and image processing, and embedded software.
