2nd Edition

Electronic Design Automation for IC System Design, Verification, and Testing

ISBN 9781138586000
Published March 29, 2018 by CRC Press
664 Pages 15 Color & 239 B/W Illustrations

USD $89.95

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Book Description

The first of two volumes in the Electronic Design Automation for Integrated Circuits Handbook, Second Edition, Electronic Design Automation for IC System Design, Verification, and Testing thoroughly examines system-level design, microarchitectural design, logic verification, and testing. Chapters contributed by leading experts authoritatively discuss processor modeling and design tools, using performance metrics to select microprocessor cores for integrated circuit (IC) designs, design and verification languages, digital simulation, hardware acceleration and emulation, and much more.

New to This Edition:

  • Major updates appearing in the initial phases of the design flow, where the level of abstraction keeps rising to support more functionality with lower non-recurring engineering (NRE) costs
  • Significant revisions reflected in the final phases of the design flow, where the complexity due to smaller and smaller geometries is compounded by the slow progress of shorter wavelength lithography
  • New coverage of cutting-edge applications and approaches realized in the decade since publication of the previous edition—these are illustrated by new chapters on high-level synthesis, system-on-chip (SoC) block-based design, and back-annotating system-level models

Offering improved depth and modernity, Electronic Design Automation for IC System Design, Verification, and Testing provides a valuable, state-of-the-art reference for electronic design automation (EDA) students, researchers, and professionals.

Table of Contents


Luciano Lavagno, Grant E. Martin, Louis K. Scheffer, and Igor L. Markov

Integrated Circuit Design Process and Electronic Design Automation
Robert Damiano, Raul Camposano, and Grant E. Martin

Tools and Methodologies for System-Level Design
Shuvra Bhattacharyya and Marilyn Wolf

System-Level Specification and Modeling Languages
Stephen A. Edwards and Joseph T. Buck

SoC Block-Based Design and IP Assembly
Yaron Kashai

Performance Evaluation Methods for Multiprocessor System-on-Chip Design
Ahmed Jerraya and Iuliana Bacivarov

System-Level Power Management
Naehyuck Chang, Enrico Macii, Massimo Poncino, and Vivek Tiwari

Processor Modeling and Design Tools
Anupam Chattopadhyay, Nikil Dutt, Rainer Leupers, and Prabhat Mishra

Models and Tools for Complex Embedded Software and Systems
Marco Di Natale


Using Performance Metrics to Select Microprocessor Cores for IC Designs
Steve Leibson

High-Level Synthesis
Felice Balarin, Alex Kondratyev, and Yosinori Watanabe


Back-Annotating System-Level Models
Miltos D. Grammatikakis, Antonis Papagrigoriou, Polydoros Petrakis, and Marcello Coppola

Microarchitectural and System-Level Power Estimation and Optimization
Enrico Macii, Renu Mehra, Massimo Poncino, and Robert P. Dick

Design Planning
Ralph H.J.M. Otten

Design and Verification Languages
Stephen A. Edwards

Digital Simulation
John Sanguinetti

Leveraging Transaction-Level Models in an SoC Design Flow
Laurent Maillet-Contoz, Jérôme Cornet, Alain Clouard, Eric Paire, Antoine Perrin, and Jean-Philippe Strassen


Assertion-Based Verification
Harry Foster and Erich Marschner

Hardware-Assisted Verification and Software Development
Frank Schirrmeister, Mike Bershteyn, and Ray Turner

Formal Property Verification
Limor Fix, Ken McMillan, Norris Ip, and Leopold Haller


Bernd Koenemann and Brion Keller

Automatic Test Pattern Generation
Kwang-Ting (Tim) Cheng, Li-C. Wang, Huawei Li, and James Chien-Mo Li

Analog and Mixed-Signal Test
Haralampos-G. Stratigopoulos and Bozena Kaminska

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Luciano Lavagno received his PhD in electrical engineering and computer sciences from the University of California, Berkeley, USA (UC Berkeley), in 1992, and from Politecnico di Torino, Italy, in 1993. He is a coauthor of two books on asynchronous circuit design, a book on hardware/software codesign of embedded systems, more than 200 scientific papers, and 12 US patents. Between 1993 and 2000, he was the architect of the POLIS project, a cooperation between UC Berkeley, Cadence Design Systems, Magneti Marelli, and Politecnico di Torino, which developed a complete hardware/software codesign environment for control-dominated embedded systems. Between 2003 and 2014, he was one of the creators and architects of the Cadence C-to-Silicon high-level synthesis system. Since 2011, he has been a full professor with Politecnico di Torino. He has been serving on the technical committees of several international conferences, workshops, and symposia. He has been the technical program chair of the Design Automation Conference, and the technical program committee and general chair of the International Conference on Hardware/Software Codesign and System Synthesis. He has been an associate editor of the Institute of Electrical and Electronics Engineers (IEEE) Transactions on Circuits and Systems and Association for Computing Machinery (ACM) Transactions on Embedded Computing. He is a senior member of the IEEE. His research interests include the synthesis of asynchronous low-power circuits, the concurrent design of mixed hardware and software embedded systems, the high-level synthesis of digital circuits, the design and optimization of hardware components and protocols for wireless sensor networks (WSNs), and design tools for WSNs.

Igor L. Markov is currently on leave from the University of Michigan, Ann Arbor, USA, where he taught for many years. He joined Google in 2014 and occasionally teaches very-large-scale integration design at Stanford University, California, USA. He researches computers that make computers, including algorithms and optimization techniques for electronic design automation, secure hardware, and emerging technologies. He is an Institute of Electrical and Electronics Engineers (IEEE) fellow and an Association for Computing Machinery (ACM) distinguished scientist. He has coauthored five books, and has four U.S. patents and more than 200 refereed publications, some of which were honored by best-paper awards. Professor Markov is a recipient of the Design Automation Conference Fellowship, ACM Special Interest Group on Design Automation Outstanding New Faculty Award, National Science Foundation Faculty Early Career Development Program Award, IBM Partnership Award, Microsoft A. Richard Newton Breakthrough Research Award, and IEEE Council on Electronic Design Automation Early Career Award. During the 2011 redesign of the ACM Computing Classification System, Professor Markov led the effort on the hardware tree. Twelve doctoral dissertations were defended under his supervision; three of which received outstanding dissertation awards.

Grant E. Martin is a distinguished engineer at Cadence Design Systems, Inc., San Jose, California, USA. Before that, Grant worked for Burroughs in Scotland for 6 years; Nortel/Bell-Northern Research in Canada for 10 years; Cadence Design Systems for 9 years, eventually becoming a fellow in their labs; and Tensilica for 9 years. He rejoined Cadence in 2013 when it acquired Tensilica, and has been there since, working in the Tensilica part of the Cadence Intellectual Property Group. He received his bachelor’s and master’s degrees in mathematics (combinatorics and optimization) from the University of Waterloo, Ontario, Canada, in 1977 and 1978. Grant has coauthored and coedited several books, including the first-ever book on system-on-chip (SoC) design published in Russian. He has also presented many papers, talks, and tutorials, and participated in panels at a number of major conferences. He cochaired the VSI Alliance Embedded Systems Study Group in the summer of 2001, and was cochair of the Design Automation Conference Technical Program Committee for Methods for 2005 and 2006. He is also a coeditor of the Springer Embedded Systems series. His particular areas of interest include system-level design, intellectual property-based design of SoC, platform-based design, digital signal processing, baseband and image processing, and embedded software. He is a senior member of the Institute of Electrical and Electronics Engineers.

Louis K. Scheffer received his BS and MS from the California Institute of Technology, Pasadena, USA, in 1974 and 1975, and his PhD from Stanford University, California, USA, in 1984. He worked at Hewlett Packard from 1975 to 1981 as a chip designer and computer-aided design tool developer. In 1981, he joined Valid Logic Systems, where he did hardware design, developed a schematic editor, and built an integrated circuit layout, routing, and verification system. In 1991, Valid merged with Cadence Design Systems, after which Dr. Scheffer worked on place and route, floorplanning systems, and signal integrity issues until 2008. In 2008, Dr. Scheffer switched fields to neurobiology, studying the structure and function of the brain by using electron microscope images to reconstruct its circuits. He is currently affiliated with the Howard Hughes Medical Institute, Ashburn, Virginia, USA. As electronic design automation (EDA) is no longer his daily staple (though his research uses a number of algorithms derived from EDA), he is extremely grateful to Igor Markov for taking on this portion of these books. Lou is also interested in the Search for Extraterrestrial Intelligence (SETI), serves on the technical advisory board for the Allen Telescope Array at the SETI Institute, and has coauthored the book SETI-2020, in addition to several technical articles in the field.


Praise for the Electronic Design Automation for Integrated Circuits Handbook, Second Edition – Two-Volume Set

"… contains the most up-to-date nuts and bolts of the front-end and back-end design automations. … covers every single EDA aspect imaginable in vivid detail. … This book will be very useful for master’s and PhD students who are doing their theses in IC design. … This is by far the most comprehensive book on EDA in the market. Every IC design company should purchase this book as a reference for their engineers."
—Faisal Mohd-Yasin, Griffith University, Queensland, Australia

"… comprehensive coverage of all aspects of algorithms and EDA tools for modern VLSI design, starting from system design to GDSII tape out, including testing. ... Practicing engineers and graduate and undergraduate students will find these two volumes to be sources of extensive knowledge. … This book is well written with in-depth explanation of basic concepts as well as advanced topics."
—Dr. Soumya Pandit, Institute of Radio Physics and Electronics, University of Calcutta, India