3rd Edition
Electronic Design Automation for Integrated Circuits Handbook Volume 1
Chapter 1 Overview
Luciano Lavagno, Grant E. Martin, Louis K. Scheffer, and Igor L. Markov
Chapter 2 Integrated Circuit Design Process and Electronic Design Automation
Robert Damiano, Raul Camposano, and Grant E. Martin
Section I — System Level Design
Chapter 3 Tools and Methodologies for System‑Level Design
Shuvra S. Bhattacharyya and Marilyn Wolf
Chapter 4 System‑Level Specification and Modeling Languages
Stephen A. Edwards and Joseph T. Buck
Chapter 5 SoC Block‑Based Design and IP Assembly
Yaron Kashai
Chapter 6 Performance Evaluation Methods for Multiprocessor System‑on‑Chip Designs
Ahmed Jerraya and Iuliana Bacivarov
Chapter 7 System‑Level Power Management
Naehyuck Chang, Enrico Macii, Massimo Poncino, and Vivek Tiwari
Chapter 8 Processor Modeling and Design Tools
Anupam Chattopadhyay, Nikil Dutt, Rainer Leupers, Prabhat Mishra, Lennart M. Reimann, Niko Zurstrasen, Zheng Wang, and Grant Martin
Chapter 9 Models and Tools for Complex Embedded Software and Systems
Marco Di Natale and Haibo Zeng
Chapter 10 Using Performance Metrics to Select Microprocessor Cores for IC Designs
Steve Leibson
Chapter 11 High‑Level Synthesis
Felice Balarin, Alex Kondratyev, Yosinori Watanabe, and Jason Cong
Section II — Micro-Architecture Design
Chapter 12 SystemC Models and Annotations
Miltos D. Grammatikakis, George Kornaros, Li Wenzhen, Brent Sherman, Antonis Papagrigoriou, Polydoros Petrakis, and Marcello Coppola
Chapter 13 Micro‑Architectural and System‑Level Power Estimation and Optimization
Enrico Macii, Renu Mehra, Massimo Poncino, and Robert P. Dick
Chapter 14 Design Planning
Ralph H.J.M. Otten
Section III — Logic Verification
Chapter 15 Design and Verification Languages
Stephen A. Edwards
Chapter 16 Digital Simulation
John Sanguinetti
Chapter 17 Gearing up with Digital Twins: From SoC Shift Left to System‑of‑Systems Quality
Laurent Maillet‑Contoz, Jerome Cornet, Alain Clouard, Eric Paire, and Jean‑Philippe Strassen
Chapter 18 Assertion‑Based Verification
Harry Foster and Erich Marschner
Chapter 19 Hardware‑Assisted Verification and Software Development
Frank Schirrmeister, Mike Bershteyn, and Ray Turner
Chapter 20 Formal Property Verification
Limor Fix, Ken McMillan, Gianpiero Cabodi, Marco Palena, Paolo Pasini, Norris Ip, and Leopold Haller
Section IV — Test
Chapter 21 Design‑for‑Test
Bernd Koenemann and Brion Keller
Chapter 22 Automatic Test Pattern Generation
Kwang‑Ting (Tim) Cheng, Li‑C. Wang, Huawei Li, and James Chien‑Mo Li
Chapter 23 Analog and Mixed‑Signal Test
Haralampos‑G. Stratigopoulos and Bozena Kaminska
Biography
Luciano Lavagno received his Ph.D. in EECS from U.C. Berkeley in 1992 and from Politecnico di Torino in 1993. He co-authored two books on asynchronous circuit design, a book on hardware/software co-design of embedded systems, and over 250 scientific papers. Between 1993 and 2000 he was the architect of the POLIS project, a cooperation between U.C. Berkeley, Cadence Design Systems, Magneti Marelli and Politecnico di Torino, which developed a complete hardware/software co-design environment for control-dominated embedded systems. Between 2003 and 2014 he was one of the creators and architects of the Cadence CtoSilicon high-level synthesis system. Since 2011, Dr. Lavagno has been a full professor with Politecnico di Torino, Italy. He has served on the technical committees of several international conferences in his field (e.g. DAC, DATE, ICCAD, ICCD, ASYNC, CODES) as well as various workshops and symposia and is a senior member of IEEE. He has also been an associate editor of IEEE TCAS and ACM TECS. His research interests include the high-level synthesis of digital circuits and the acceleration of Machine learning algorithms using Field Programmable Gate Arrays.
Grant E. Martin retired from his position as a distinguished engineer at Cadence Design Systems, Inc., San Jose, California, USA, in 2023. Before that, Grant worked for Burroughs in Scotland for 6 years; Nortel/Bell-Northern Research in Canada for 10 years; Cadence Design Systems for 9 years, eventually becoming a fellow in their labs; and Tensilica for 9 years. He rejoined Cadence in 2013 when it acquired Tensilica, and has been there since, working in the Tensilica part of the Cadence Intellectual Property Group. He received his bachelor’s and master’s degrees in mathematics (combinatorics and optimization) from the University of Waterloo, Ontario, Canada, in 1977 and 1978. Grant has coauthored and coedited several books, including the first-ever book on system-on-chip (SoC) design published in Russian. He has also presented many papers, talks, and tutorials, and participated in panels at several major conferences. He cochaired the VSI Alliance Embedded Systems Study Group in the summer of 2001 and was co-chair of the Design Automation Conference Technical Program Committee for Methods for 2005 and 2006. He is a senior member of IEEE. Although retired, he continues to have an interest in system-level design, IP-based design of system-on-chip, platform-based design, DSP, baseband and image processing, and embedded software.
