Rapid energy estimation for energy efficient applications using field-programmable gate arrays (FPGAs) remains a challenging research topic. Energy dissipation and efficiency have prevented the widespread use of FPGA devices in embedded systems, where energy efficiency is a key performance metric. Helping overcome these challenges, Energy Efficient Hardware-Software Co-Synthesis Using Reconfigurable Hardware offers solutions for the development of energy efficient applications using FPGAs.
The book integrates various high-level abstractions for describing hardware and software platforms into a single, consistent application development framework, enabling users to construct, simulate, and debug systems. Based on these high-level concepts, it proposes an energy performance modeling technique to capture the energy dissipation behavior of both the reconfigurable hardware platform and the target applications running on it. The authors also present a dynamic programming-based algorithm to optimize the energy performance of an application running on a reconfigurable hardware platform. They then discuss an instruction-level energy estimation technique and a domain-specific modeling technique to provide rapid and fairly accurate energy estimation for hardware-software co-designs using reconfigurable hardware. The text concludes with example designs and illustrative examples that show how the proposed co-synthesis techniques lead to a significant amount of energy reduction.
This book explores the advantages of using reconfigurable hardware for application development and looks ahead to future research directions in the field. It outlines the range of aspects and steps that lead to an energy efficient hardware-software application synthesis using FPGAs.
Challenges and Contributions
Reconfigurable System-on-Chips (RSoCs)
A High-Level Hardware-Software Application Development Framework
An Implementation Based on MATLAB/Simulink
Energy Performance Modeling and Energy Efficient Mapping for a Class of Applications
Knobs for Energy Efficient Designs
Performance Modeling of RSoC Architectures
Algorithm for Energy Minimization
High-Level Rapid Energy Estimation and Design Space Exploration
A Two-Step Rapid Energy Estimation Technique
Energy Estimation for Customized Hardware Components
Instruction-Level Energy Estimation for Software Programs
Hardware-Software Co-Design for Energy Efficient Implementations of Operating Systems
Real-Time Operating Systems
On-Chip Energy Management Mechanisms
An Implementation Based on MicroC/OS-II
An Implementation Based on TinyOS
Concluding Remarks and Future Directions