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Graphene and VLSI Interconnects



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ISBN 9789814877824
November 25, 2021 Forthcoming by Jenny Stanford Publishing
126 Pages 17 Color & 40 B/W Illustrations

 
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Book Description

Copper (Cu) is used as an interconnection material in semiconductor industries for years owing to its best balance of conductivity and performance. However, it is running out of steam as it is approaching its limits with respect to electrical performance and reliability. Graphene is a non-metal material, but it can help to improve electromigration (EM) performance of Cu owing to its excellent properties. Combining graphene with copper for VLSI interconnects can be a viable solution. The incorporation of graphene into Cu allows the present Cu fabrication back-end process to remain unaltered, except the small step of "inserting" graphene into Cu. Therefore, it has a great potential to revolutionize the VLSI-IC industry and appeal for further advancement of semiconductor industry. This book is a compilation of comprehensive studies done on the properties of graphene and its synthesis methods suitable for VLSI interconnects’ applications. It includes the development of a new method to synthesize graphene, the evaluation of electrical and EM performance of graphenated Cu interconnects, and a new graphene-based electroless deposition method for Cu and other metals.

Table of Contents

1. Graphene-Copper Handshake

1.1. Importance of Interconnections in VLSI

1.2. Copper is Running Out of Steam

1.3. Graphene As a Solution

1.4. Properties and Applications of Graphene

1.5. Summary

References

2. Graphene Synthesis Methods

2.1. An overview of the existing methods

2.2. Drawbacks of Current Methods with Respect to Applications in VLSI Interconnect Fabrication

2.3. Summary

References

3. Novel and Improved Graphene Synthesis Method

3.1. Exploration of Carbon Sources

3.2. Amorphous Carbon As a Promising Candidate: A PVD-Based Synthesis

3.3. Growth Mechanism of PVD-Based Graphene

3.4. Summary

References

4. Statistical Approach to Identify Key Growth Parameters of the Novel Graphene Growth PVD Processes

4.1. Brief History and Need of DoE

4.2. Importance of DoE

4.3. Applications of DoE

4.4. Illustration of DoE for the Novel PVD Graphene Synthesis

4.5. Summary of Graphene Growth using DoE

References

5. Copper–Graphene Interconnect

5.1. Introduction

5.2. Electrical and Thermal Characteristics of Graphenated Copper

5.3. Compatibility of Graphenated Interconnect to Current-Integrated Circuit Back End Processes

5.4. A Novel Copper–Graphene–Copper Interconnect and Its Potential Performance

5.5. Mechanism of Electroless Cu Deposition on Graphenated Cu

5.6. Summary

References

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Author(s)

Biography

Cher-Ming Tan is director of the Center for Reliability Sciences and Technologies (CReST) and a professor at the Department of Electronic Engineering as well as the Institute of Radiation Research, College of Medicine, Chang Gung University, Taoyuan, Taiwan. He is an honorary chair professor at the Center of Reliability Engineering, Ming Chi University of Technology, Taiwan, and a researcher at the Department of Urology, Chang Gung Memorial Hospital, Taoyuan, Taiwan. He earned his PhD (1992) in electrical engineering from the University of Toronto, Ontario, Canada. He joined Nanyang Technological University, Singapore, as a faculty member in 1997, and Chang Gung University in 2014. His research interests include materials analysis, failure analysis, reliability of electronics devices, reliability of system, reliability statistics, modeling, and simulation.

Udit Narula is a postdoctoral research fellow at CReST. He completed his BTech (2011) from Maharshi Dayanand University, Haryana, India, and MTech (2013) from Amity University, Noida, India. He earned his PhD from the Department of Electronic Engineering, Chang Gung University. His research interests include graphene-based ULSI interconnects, graphene synthesis methods, and component/system reliability analysis and statistics.

Vivek Sangwan is a postdoctoral research fellow at CReST. He completed his BTech (2012) from Dr. A.P.J. Abdul Kalam Technical University, Lucknow, India and MTech (2014) from Amity University, Noida, India. He earned his PhD (2019) from the Department of Electronic Engineering, Chang Gung University. His research interests include failure and reliability analysis of integrated circuits, design of experiments, and design and simulation of 3D models.