The drive toward smaller and smaller electronic componentry has huge implications for the materials currently being used. As quantum mechanical effects begin to dominate, conventional materials will be unable to function at scales much smaller than those in current use. For this reason, new materials with higher electrical permittivity will be required, making this is a subject of intensive research activity within the microelectronics community.
High k Gate Dielectrics reviews the state-of-the-art in high permittivity gate dielectric research. Consisting of contributions from leading researchers from Europe and the USA, the book first describes the various deposition techniques used for construction of layers at these dimensions. It then considers characterization techniques of the physical, chemical, structural, and electronic properties of these materials. The book also reviews the theoretical work done in the field and concludes with technological applications.
"High-K Gate Dielectrics is a timely review of this rapidly evolving research field. The individual chapters provide a complete, in-depth coverage of current understanding, making the book an excellent source of reference for researchers in High-K gate dielectrics and … newcomers to the field. The impressive work and methods … should make the book of interest for a readership beyond those immediately involved in high-k gate dielectric research. I recommend the book as a very good reference source and overview to researchers with interest in high-k gate dielectrics."
-Susanne Stemmer, Materials Today, September 2004
The need for high-k gate dielectrics and materials requirement
ALCVD, MOCVD, PLD, MBE
X-ray and electron spectroscopies
Oxygen diffusion and thermal stability
Defect characterization by ESR
Band alignment determined by photo-injection
Theory of defects in high-k materials
Bonding constraints and defect formation at Si/high-k interfaces
Band alignment calculations
Electron mobility at the Si/high-k interface
Model for defect generation during electrical stress
Device integration issues
Device concepts for sub-100 nm CMOS technologies
Nonvolatile memories based on high-k ferroelectric layers