Introduction to Microelectronics to Nanoelectronics : Design and Technology book cover
1st Edition

Introduction to Microelectronics to Nanoelectronics
Design and Technology

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ISBN 9780367502379
November 25, 2020 Forthcoming by CRC Press
352 Pages - 243 B/W Illustrations

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Book Description

Focussing on micro- and nanoelectronics design and technology, this book provides thorough analysis and demonstration, starting from semiconductor devices to VLSI fabrication, designing (analog and digital), on-chip interconnect modeling culminating with emerging non-silicon/ nano devices. It gives detailed description of both theoretical as well as industry standard HSPICE, Verilog, Cadence simulation based real-time modeling approach with focus on fabrication of bulk and nano-devices. Each chapter of this proposed title starts with a brief introduction of the presented topic and ends with a summary indicating the futuristic aspect including practice questions. Aimed at researchers and senior undergraduate/graduate students in electrical and electronics engineering, microelectronics, nanoelectronics and nanotechnology, this book:

  • Provides broad and comprehensive coverage from Microelectronics to Nanoelectronics including design in analog and digital electronics.
  • Includes HDL, and VLSI design going into the nanoelectronics arena.
  • Discusses devices, circuit analysis, design methodology, and real-time simulation based on industry standard HSPICE tool.
  • Explores emerging devices such as FinFETs, Tunnel FETs (TFETs) and CNTFETs including their circuit co-designing.
  • Covers real time illustration using industry standard Verilog, Cadence and Synopsys simulations.

Table of Contents

1.1 Introduction
1.1.1 Conduction in Solids
1.1.2 Conductors, Semiconductors, and Insulator
1.1.3 P-Type and N-Type Semiconductors
     1.1.4      Semiconductor Conductivity
1.2  Diodes
1.2.1 Diode Structure and Characteristics
1.2.2 PN Diode Structure
1.2.3 Zener Diode Structure
1.2.4 Diode Applications
1.3 Bipolar Junction Transistors
1.3.1 Symbol and Physical Structure
1.3.2 BJT Configuration
1.3.3 Second Order Effects
1.4 Field Effect Transistors
1.4.1 Junction Field Effect Transistors (JFET)
1.4.2 Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
1.4.3 Advantages of MOSFET over JFET
1.5 Emerging Devices beyond MOS
1.5.1 Issues with CMOS Technology Scaling
1.5.2 Emerging Nano-scale Device Technologies
1.6 Summary
1.7 Multiple Choice Questions
1.8 Short Answer Questions
1.9 Long Answer Questions
1.10 References

2.1 Introduction to VLSI Scaling
2.1.1 History and Introduction of VLSI Technology
2.1.2 VLSI Design’s Concept
2.1.3 Moore’s Law
2.1.4 Scale of Integration
2.1.5 Types of VLSI Chips ( Analog & Digital)
2.1.6 Layout, and Micron & Lambda Rules
2.2 VLSI Fabrication Process
2.2.1 Purification, Crystal Growth, and Wafer Processing (CZ and FZ Process)
2.2.2 Oxidation
2.2.3 Epitaxial Deposition
2.2.4 Lithography
2.2.5 Polysilicon and Dielectric Deposition
2.2.6 Diffusion
2.2.7 Ion Implementation
2.2.8 Metallization
2.2.9 Etching Process
2.3 Basic CMOS Technology
2.3.1 N-Well and P-Well CMOS Process
2.3.2 Twin Tub Process
2.4 Summary
2.5 Multiple Choice Questions
2.6 Short Answer Questions
2.7 Long Answer Questions
2.8 References

3.1 Introduction to MOS Transistor
3.1.1 Characteristics of MOS Transistor
3.1.2 Hot Carrier Effects
3.1.3 Parasitics of MOSFET
3.1.4 MOSFET Circuit Models
3.2 MOS Capacitor
3.2.1 MOS Capacitor with Zero and Nonzero Bias
3.2.2 Capacitance-Voltage Curves
3.2.3 Anomalous Capacitance-Voltage Curves
3.3 MOSFET DC and Dynamic Models
3.3.1 Pao-Sah Model
3.3.2 Charge Sheet Model
3.3.3 Piece-Wise Model for Enhancement Devices
3.3.4 Small Geometry Model
3.3.5 Intrinsic Charge and Capacitance
3.3.6 Meyer Model
3.4 MOSFET Modeling using SPICE
3.4.1 Basic Concepts of Modeling
3.4.2 Model Equations
3.4.3 Examples using HSPICE
3.5 Summary
3.6 Multiple Choice Questions
3.7 Short Answer Questions
3.8 Long Answer Questions
3.9 References

4.1 CMOS Inverter
4.1.1 Design
4.1.2 Operation
4.1.3 Transient and VTC Characteritsitics
4.1.4 Significance of CMOS Inverter
4.2  Static Behavior of Inverter
4.2.1 Switching Threshold
4.2.2 Noise Margin
4.2.3 Robustness of CMOS inverter by scaling supply voltage
4.3 Dynamic behavior of CMOS inverter
4.3.1 Capacitances
4.3.2 Power and Energy consumption
4.4 Design of Combinational Logic Design
4.4.1 Complementary CMOS logic
4.4.2 Ratioed Logic
4.4.3 Pass-Transistor Logi
4.5 CMOS Sequential Design
4.5.1 Introduction
4.5.2 Metrics for CMOS Sequential Design
4.6 Static Latches and  Registers
4.6.1 The Bistability Principle
4.6.2 SR Flip-Flops
4.6.3 D-latches and Flip-Flops
4.6.4 Master slave Flip-flop
4.7 Summary
4.8 Multiple Choice Questions
4.9 Short Questions
4.10 Long Questions
4.11 References

5.1 Introduction to Analog Design
5.2 MOS device from Analog perspective
5.2.1 I/V Characteristics
5.2.2 Second-order Effects
5.2.3 MOS Small Signal Model
5.3 Single Stage Amplifier
5.3.1 Common Source
5.3.2 Common Gate
5.3.3 Source Follower
5.4 Current mirrors
5.4.1 Introduction
5.4.2 Basic Current Mirror
5.4.3 Cascode current Mirror
5.5 Differential Amplifiers
5.5.1 Single ended and differential Operation
5.5.2 Basic Differential Pair
5.5.3 Differential Pair with MOS load
5.6 Operational Amplifiers
5.6.1 Fundamentals and General Op-amp metrics
5.6.2 Two Stage Op-amp
5.7 Digital-to-Analog and Analog-to-Digital Converters
5.7.1 Introduction
5.7.2 Types of Digital-to-Analog Converters
5.7.3 Types of Analog-to-Digital Converters
5.8 Summary
5.9 Multiple Choice Questions
5.10 Short Answer Questions
5.11 Long Answer Questions
5.12 References
6.1 Introduction
6.1.1 What is Verilog HDL
6.1.2 Backgrounnd
6.1.3 Compiler Directives
6.1.4 Data Types
6.1.5 Operators
6.2 Module and Test bench Definitions
6.2.1 Module
6.2.2 Test bench
6.3 Gate-Level Modeling
6.3.1 Built-in primitives
6.3.2 Single and multiple input gates
6.3.3 Tristate gates
6.3.4 MOS Switch
6.3.5 Gate Delays
6.3.6 Example
6.4   Dataflow Modeling
6.4.1 Continuous Assignments
6.4.2 Delays
6.4.3 Examples: Verilog Program for Full Adder
6.5   Behavioral Modeling
6.5.1 Initial Statement
6.5.2 Always Statement
6.5.3 Procedural Assignments
6.5.4 Conditional Statements
6.5.5 Loop Statements
6.5.6 Examples
6.6   Tasks and Functions
6.6.1 Tasks
6.6.2 Functions
6.7 Summary
6.8 Multiple Choice Questions
6.9 Short Questions
6.10 Long Questions
6.11 References

7.1 An overview of the VLSI Interconnect Problem
7.1.1 Interconnect Scaling Problem
7.1.2 Implementation of Interconnect Problem
7.2 Interconnect Aware Design Methodology and Electrical Modeling
7.2.1 Impact of Scaling
7.2.2 Transistor Scaling
7.2.3 Interconnect Scaling
7.3 Electrical Circuit Model of Interconnect
7.3.1 Ideal Interconnect
7.3.2 Resistive Interconnect
7.3.3 Capacitive Interconnect
7.3.4 Resistive Interconnect Tree
7.4 Estimation of Interconnect Parasitics
7.4.1 Interconnect Resistance Estimation
7.4.2 Interconnect Inductance Estimation
7.4.3 Interconnect Capacitance Estimation Parallel Plate Capacitor Fringing Capacitance Lateral Capacitance
7.5 Calculation of Interconnect Delay
7.5.1 RC Delay Model
7.5.2 Elmore Delay Model
7.5.3 Transfer Function Model based on ABCD Parameter matrix
7.5.4 Finite Difference Time Domain Model (FDTD)
7.6 Estimation of Interconnect Crosstalk Noise
7.7 Estimation of Interconnect Power Dissipation
7.8 Summary
7.9 Multiple Choice Questions
7.10 Short Answer Questions
7.11 Long Answer Questions
7.12 References

8.1 Preamble
8.2 Basic Digital Troubleshoot 
8.2.1 Manufacturing Test
8.2.2 Tester and Test Fixtures
8.2.3 Test Programs
8.3 Effect of Physical Faults on Circuit Behavior
8.3.1 Fault Models Line Stuck-at Faults Transistor Stuck-at Faults Floating Line Faults Bridging Faults
8.4 Test Principles of Manufacturing
8.4.1 Observability
8.4.2 Controllability
8.4.3 Fault Coverage
8.4.4 Automatic Test Pattern Generation (ATPG)
8.4.5 Delay Fault Testing
8.5 Test Approaches
8.5.1 Ad Hoc DFT Techniques
8.5.2 Scan Design Test
8.5.3 Built-in-Self-Test (BIST)
8.5.4 IDDQ Testing
8.6   Design for Manufacturability (DFM)
8.7   System on Chip (SOC) Testing
8.8   Summary
8.9 Multiple Choice Questions
8.10 Short Answer Questions
8.11 Long Questions
8.12 References

9.1 Preamble of Nano-Materials
9.2 Introduction to Carbon Nanotubes (CNTs)
9.2.1 The concept of Chirality on CNT
9.2.2 Electronic Band Structure
9.2.3 Brillouin zone
9.3 Overview of Graphene Nanoribbon (GNR)
9.4 Properties of CNT and GNR
9.5 Fabrication Approaches for Graphene Nanostructure
9.5.1 The transfer process of graphene on the Si/SiO2 substrate
9.5.2 CNT Fabrications
9.6 Application of Nano-materials
9.6.1 Graphene Nanoribbon Interconnect
9.6.2 Carbon Nanotube based Interconnect
9.6.3 Nano-Sensor
9.6.4 Nanomaterial Based Combat Jacket
9.6.5 Nano Bio-Sensor for Drug Delivery
9.7      Summary
9.8 Multiple Choice Questions
9.9 Short Answer Questions
9.10 Long Answer Questions
9.11 References

10.1 Issues with CMOS technology scaling
10.1.1 Velocity Saturation and Mobility Degradation
10.1.2 Tunneling Limit
10.1.3 High Field Effects
10.1.4 Power Limitation
10.1.5 Material limitation
10.2 Tunnel FET
10.2.1 Device Structure and Models
10.2.2 Device Characteristics
10.2.3 TFET based Circuit design
10.3 Negative Capacitance FET
10.3.1 Device Structure
10.3.2 Principle of operation
10.3.3 Low subthreshold swing and high ON current
10.3.4 Hysteresis Characteristics
10.3.5 NCFET device based inverter and digital logic design
10.4 Carbon Nanotube FET
10.4.1 Carbon nanotube (CNT)
                    10.4.2  Carbon nanotube FET (CNTFET)
10.4.2 Device Characteristics
10.5 Graphene Nanoribbon FET
10.5.1 Graphene structure and properties
10.5.2 Graphene nanoribbon FET (GNRFET)
10.6 Spintronic Devices
10.6.1 Principle of Operation
10.6.2 Spin based Devices
10.7 Summary
10.8 Multiple Choice Questions
10.9 Short Answer Questions
10.10 Long Answer Questions
10.11 References


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Manoj Kumar Majumder received his PhD from Microelectronics and VLSI group at Indian Institute of Technology, Roorkee, India. Currently, he is working as assistant professor in Department of Electronics and Communication Engineering, IIIT Naya Raipur, Chhattisgarh. He has authored more than 25 papers in peer-reviewed international journals and more than 40 papers in international conferences. He has co-authored a book titled Carbon Nanotobe Based VLSI Interconnects-Analysis and Design (New York, NY, USA: Springer, 2014) and a book-chapter published by CRC Press. His current research interests include the area of graphene based Low power VLSI devices and circuits, On-chip VLSI interconnects and Through silicon vias. Dr. Majumder is associated with different academic and administrative activities of different positions in IIIT, Naya Raipur. He is an active member of IEEE, IEEE Electron Device Society and IEEE Circuits and Systems Society. He had delivered technical talks at different conferences in India and abroad. He is also an active reviewer of IEEE Transactions on electromagnetic Compatibility, IEEE Transactions on Nanotechnology, IEEE Electron Device Letters, Microelectronics Journal, IET Micro & Nano Letters, and other Springer Journals. He is a Member of many expert committees constituted by Government and Nongovernment organizations. He has also received many awards and recognitions from International Biographical Center, Cambridge, etc. His name has been listed in Marquis Who’s Who in the World. Vijay Rao Kumbhare received the B.Tech degree in Electronics and Telecommunication Engineering from National Institute of Technology, Raipur, India in 2008, and M.Tech degree with specialization of Telecommunication System Engineering (TSE) under Electronics and Engineering Communication Department from Indian Institute of Technology, Kharagpur, West Bengal, India, in 2011. He had worked experience as assistant professor more than 5 years. He is currently working toward the Ph.D degree from Dr. Shyama Prasad Mukherjee International Institute of Information Technology Naya Raipur, India. He has attended several workshop and conferences, along with an active reviewer of reputed IET Biotechnology. His current research interest are in the area of Graphene nanoribbon, Carbon nanotube and optical based On-chip VLSI interconnects, emerging nano-materials. Aditya Japa received B.Tech. degree in Electronics and Communication Engineering from Sree Chaitanya College of Engineering, Karimnagar (J.N.T.U Hyderabad), Telangana, India, in 2012 and the M.Tech. degree in VLSI Design from Vignan’s University, Andhra Pradesh, India, in 2015. He was a JRF under a DST project titled “Design, Analysis and Benchmarking of Energy efficient Hetero-junction tunnel FET based Digital, Analog and RF Building blocks during 2015-16. He is currently pursuing Ph.D. in Electronics and Communication Engineering from DSPM International Institute of Information Technology, Naya Raipur, India. His current research interest includes Hardware security subsystems like TRNG and PUF, emerging transistor technologies (Tunnel FETs), ultra-low power/energy efficient sensor readout circuits, VLSI design etc. Brajesh Kumar Kaushik received his Doctorate of Philosophy (Ph.D.) in 2007 from Indian Institute of Technology, Roorkee, India. He joined Department of Electronics and Communication Engineering, Indian Institute of technology, Roorkee, as Assistant Professor in December 2009; and since April 2014 he has been an Associate Professor. He has extensively published in several national and international journals and conferences. He is a reviewer of many international journals belonging to various publishers including IEEE, IET, Elsevier, Springer, Taylor & Francis, Emerald, ETRI, and PIER. He has served as General Chair, Technical Chair, and Keynote Speaker of many reputed international and national conferences. Dr. Kaushik is Senior Member of IEEE and member of many expert committees constituted by government and non-government organizations. He holds the position of Editor and Editor-in-Chief of various journals in the field of VLSI and microelectronics such as International Journal of VLSI Design & Communication Systems (VLSICS), AIRCC Publishing Corporation. He also holds the position of Editor of Microelectronics Journal (MEJ), Elsevier Inc.; Journal of Engineering, Design and Technology (JEDT), Emerald Group Publishing Limited; Journal of Electrical and Electronics Engineering Research (JEEER); and Academic Journals. He has received many awards and recognitions from the International Biographical Center (IBC), Cambridge. His name has been listed in Marquis Who’s Who in Science and Engineering® and Marquis Who’s Who in the World®. Dr. Kaushik has been conferred with Distinguished Lecturer award of IEEE Electron Devices Society (EDS) to offer EDS Chapters with a list of quality lectures in his research domain.