1st Edition
Memory Management for Synthesis of DSP Software
320 Pages
107 B/W Illustrations
by
CRC Press
320 Pages
107 B/W Illustrations
by
CRC Press
Also available as eBook on:
Although programming in memory-restricted environments is never easy, this holds especially true for digital signal processing (DSP). The data-rich, computation-intensive nature of DSP makes memory management a chief and challenging concern for designers. Memory Management for Synthesis of DSP Software focuses on minimizing memory requirements during the synthesis of DSP software from dataflow... Read more
INTRODUCTION
Electronic Embedded Systems
Digital Signal Processing Systems
Actor-Oriented Design
Dataflow MoCs for DSP Systems
Synthesis Techniques in AOPEs
Advances in Compilers for DSPs
Other Related Work-Nested Loop Scheduling
NOTATION AND BACKGROUND
Graph Terminology
Synchronous Dataflow
Synthesis from SDF Graphs
Scheduling Problems for SDF Graphs
Constructing Memory-Efficient Loop Structures
Scheduling for Other Metrics
Other Topics: Holes
Summary
LIFETIME ANALYSIS
Introduction
The Shared Buffer Model
Creating the Interval Instances from a SAS
Conclusion
DYNAMIC STORAGE ALLOCATION
Some Notation
Heuristic for DSA
Computing the Maximum Clique Weight
Experimental Results
Approximation Algorithms
THE CBP PARAMETER
Related Work
Introduction to Buffer Merging
The CBP Parameter
Multirate FIR Filters
Chop
Autocorrelation
CBP Tables
Summary of Derivations
Conclusion
BUFFER SHARING VIA MERGING TECHNIQUES
Merging an Input/Output Buffer Pair
Merging a Chain of Buffers
A Heuristic for Merged Cost-Optimal SAS
Conclusion
BUFFER MERGING ALGORITHMS
Acyclic Graphs
Experimental Results
Conclusion
BEYOND SINGLE APPEARANCE SCHEDULES
Recursive Decomposition of a Two-Actor SDF Graph
Extension to Arbitrary SAS
CD-DAT Example
Experimental Results
Conclusion
CONCLUSION
Regularity
Fixed-Point Optimizations
Reconfigurable Systems
Grand Challenge
REFERENCES
INDEX
Electronic Embedded Systems
Digital Signal Processing Systems
Actor-Oriented Design
Dataflow MoCs for DSP Systems
Synthesis Techniques in AOPEs
Advances in Compilers for DSPs
Other Related Work-Nested Loop Scheduling
NOTATION AND BACKGROUND
Graph Terminology
Synchronous Dataflow
Synthesis from SDF Graphs
Scheduling Problems for SDF Graphs
Constructing Memory-Efficient Loop Structures
Scheduling for Other Metrics
Other Topics: Holes
Summary
LIFETIME ANALYSIS
Introduction
The Shared Buffer Model
Creating the Interval Instances from a SAS
Conclusion
DYNAMIC STORAGE ALLOCATION
Some Notation
Heuristic for DSA
Computing the Maximum Clique Weight
Experimental Results
Approximation Algorithms
THE CBP PARAMETER
Related Work
Introduction to Buffer Merging
The CBP Parameter
Multirate FIR Filters
Chop
Autocorrelation
CBP Tables
Summary of Derivations
Conclusion
BUFFER SHARING VIA MERGING TECHNIQUES
Merging an Input/Output Buffer Pair
Merging a Chain of Buffers
A Heuristic for Merged Cost-Optimal SAS
Conclusion
BUFFER MERGING ALGORITHMS
Acyclic Graphs
Experimental Results
Conclusion
BEYOND SINGLE APPEARANCE SCHEDULES
Recursive Decomposition of a Two-Actor SDF Graph
Extension to Arbitrary SAS
CD-DAT Example
Experimental Results
Conclusion
CONCLUSION
Regularity
Fixed-Point Optimizations
Reconfigurable Systems
Grand Challenge
REFERENCES
INDEX
Biography
Praveen K. Murthy, Shuvra S. Bhattacharyya
