1st Edition
Network-on-Chip The Next Generation of System-on-Chip Integration
Introduction
System-on-Chip Integration and Its Challenges
SoC to Network-on-Chip: A Paradigm Shift
Research Issues in NoC Development
Existing NoC Examples
Summary
References
Interconnection Networks in Network-on-Chip
Introduction
Network Topologies
Switching Techniques
Routing Strategies
Flow Control Protocol
Quality-of-Service Support
NI Module
Summary
References
Architecture Design of Network-on-Chip
Introduction
Switching Techniques and Packet Format
Asynchronous FIFO Design
GALS Style of Communication
Wormhole Router Architecture Design
VC Router Architecture Design
Adaptive Router Architecture Design
Summary
References
Evaluation of Network-on-Chip Architectures
Evaluation Methodologies of NoC
Traffic Modeling
Selection of Channel Width and Flit Size
Simulation Results and Analysis of MoT Network with WH Router
Impact of FIFO Size and Placement in Energy and Performance of a Network
Performance and Cost Comparison of MoT with Other NoC Structures Having WH Router under Self-Similar Traffic
Simulation Results and Analysis of MoT Network with Virtual Channel Router
Performance and Cost Comparison of MoT with Other NoC Structures Having VC Router
Limitations of Tree-Based Topologies
Summary
References
Application Mapping on Network-on-Chip
Introduction
Mapping Problem
ILP Formulation
Constructive Heuristics for Application Mapping
Constructive Heuristics with Iterative Improvement
Mapping Using Discrete PSO
Summary
References
Low-Power Techniques for Network-on-Chip
Introduction
Standard Low-Power Methods for NoC Routers
Standard Low-Power Methods for NoC Links
System-Level Power Reduction
Summary
References
Signal Integrity and Reliability of Network-on-Chip
Introduction
Sources of Faults in NoC Fabric
Permanent Fault Controlling Techniques
Transient Fault Controlling Techniques
Unified Coding Framework
Energy and Reliability Trade-Off in Coding Technique
Summary
References
Testing of Network-on- Chip Architectures
Introduction
Testing Communication Fabric
Testing Cores
Summary
References
Application-Specific Network-on-Chip Synthesis
Introduction
ASNoC Synthesis Problem
Literature Survey
System-Level Floorplanning
Custom Interconnection Topology and Route Generation
ASNoC Synthesis with Flexible Router Placement
Summary
References
Reconfigurable Network-on-Chip Design
Introduction
Literature Review
Local Reconfiguration Approach
Topology Reconfiguration
Link Reconfiguration
Summary
References
Three-Dimensional Integration of Network-on-Chip
Introduction
3-D Integration: Pros and Cons
Design and Evaluation of 3-D NoC Architecture
Summary
References
Conclusions and Future Trends
Conclusions
Future Trends
Comparison between Alternatives
References
Index
Biography
Santanu Kundu received his BTech in instrumentation engineering from Vidyasagar University, Medinipur, West Bengal, India, in 2002. He received his MTech in instrumentation and electronics engineering from Jadavpur University, Kolkata, West Bengal, India, in 2006. Immediately after that he joined the electronics and electrical communication engineering department at the Indian Institute of Technology, Kharagpur, West Bengal, India. He received his PhD in 2011. His research interests include network-on-chip architecture design in 2D and 3D environments, performance and cost evaluation, signal integrity in nanometer regime, fault-tolerant schemes, and power–performance–reliability trade-off. He is currently a system-on-chip (SoC) design engineer at LSI India R&D Pvt. Ltd., Bangalore, Karnataka, India.
Santanu Chattopadhyay
received his BE in computer science and technology from Calcutta University (BE College), Kolkata, West Bengal, in 1990. In 1992 and 1996, he received his MTech in computer and information technology and PhD in computer science and engineering, respectively, both from the Indian Institute of Technology (IIT), Kharagpur, West Bengal, India. He is currently a professor in the electronics and electrical communication engineering department at the IIT, Kharagpur. He has contributed to more than 100 publications in refereed international journals and conferences. He has also coauthored and written several textbooks, and is a member of the editorial board of the journal IET Circuits, Devices and Systems."What makes this book special as compared to the current literature in the field is that it provides a complete picture of NoC architectures. In fact, current books in the context of NoCs are usually specific and presuppose a basic knowledge of NoC architectures. Conversely, this book provides a complete guide for both unskilled readers and researchers working in the area, to acquire not only the basic concepts but also the advanced techniques for improving power, cost and performance metrics of the on-chip communication system."
—Maurizio Palesi, Kore University, Italy
