Chapter 1 Introduction
Chapter 2 Fundamentals of Verilog
Chapter 3 Advanced Verilog Topics
Chapter 4 Number Representation
Chapter 5 Combinational Circuits
Chapter 6 Sequential Circuits
Chapter 7 Digital System Designs
Chapter 8 Advanced System Designs
Chapter 9 I/O Interface Chapter
10 Logic Synthesis with Design Compiler
Appendix A Basic Logic Gates and User Defined Primitives
Appendix B Non-Synthesizable Constructs
Appendix C Advanced Net Data Types
Appendix D Signed Multipliers
Appendix E Good Coding and Naming Styles
Biography
Wen-Long Chin is a professor of Engineering Science, at the National Cheng Kung University (NCKU), Taiwan. Before holding the faculty position, he worked in the Hsinchu Science Park, Taiwan, for over 11 years, in charge of communication and network IC designs. He is a senior member of IEEE and serves as Technical Editor of IEEE Wireless Communications, and Associate Editors of IEEE Access and EURASIP Journal on Wireless Communications and Networking. He has published approximately 60 Journal and conference papers, 1 book chapter, and 14 patents.
