Reconfigurable Logic: Architecture, Tools, and Applications, 1st Edition (Hardback) book cover

Reconfigurable Logic

Architecture, Tools, and Applications, 1st Edition

Edited by Pierre-Emmanuel Gaillardon

CRC Press

526 pages | 20 Color Illus. | 216 B/W Illus.

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pub: 2015-10-28
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Description

During the last three decades, reconfigurable logic has been growing steadily and can now be found in many different fields. Field programmable gate arrays (FPGAs) are one of the most famous architecture families of reconfigurable devices. FPGAs can be seen as arrays of logic units that can be reconfigured to realize any digital systems. Their high versatility has enabled designers to drastically reduce time to market, and made FPGAs suitable for prototyping or small production series in many branches of industrial products. In addition, and thanks to innovations at the architecture level, FPGAs are now conquering segments of mass markets such as mobile communications.

Reconfigurable Logic: Architecture, Tools, and Applications offers a snapshot of the state of the art of reconfigurable logic systems. Covering a broad range of architectures, tools, and applications, this book:

  • Explores classical FPGA architectures and their supporting tools
  • Evaluates recent proposals related to FPGA architectures, including the use of network-on-chips (NoCs)
  • Examines reconfigurable processors that merge concepts borrowed from the reconfigurable domain into processor design
  • Exploits FPGAs for high-performance systems, efficient error correction codes, and high-bandwidth network routers with built-in security
  • Expounds on emerging technologies to enhance FPGA architectures, improve routing structures, and create non-volatile configuration flip-flops

Reconfigurable Logic: Architecture, Tools, and Applications reviews current trends in reconfigurable platforms, providing valuable insight into the future potential of reconfigurable systems.

Table of Contents

CLASSICAL FPGA ARCHITECTURE AND TOOLS

Adaptive Packing for Design Space Exploration of FPGA Logic Block Architectures

Jason Luu

Introduction

Prior Work

Architecture-Aware Packing

Experiments and Results

Summary and Future Work

Improving Fault Tolerance of SRAM-Based FPGAs in Harsh Radiation Environments

Heather Quinn, Keith Morgan, Paul Graham, Zachary Baker, Michael Caffrey, Diane Roussel-Dupree, Will Howes, Eric Johnson, Jon Johnson, Jim Krone, David Lee, Kevin Lundgreen, Tony Nelson, Brian Pratt, Nathan Rollins, Anthony Salazar, Gary Swift, and Michael Wirthlin

Introduction

Radiation Characterization of FPGAs

Hardness Assurance Estimates

Case Study: The Mission Response Module

Conclusions

Zero-Overhead FPGA Debugging

Eddie Hung and Steven J.E. Wilton

Introduction

Background

Trace-Based Debug

Network Flow-Based Routing

Methodology

Results

Ongoing and Future Research

Conclusion

ADVANCED ARCHITECTURAL TECHNIQUES

Tree-Based FPGA Routing Architectures

Zied Marrakchi and Habib Mehrez

Introduction

Interconnect Description

Interconnect Depopulation

Connection with Outside

Rent's Rule-Based Model

Configuration Flow

Experimental Evaluation

2D Physical Design of Tree-Based FPGA

Wire Length Optimization and Performance Improvement

Conclusion

And-Inverter Cones

Grace Zgheib, Hadi Parandeh-Afshar, David Novo, and Paolo Ienne

Introduction

And-Inverter Cone Structure

AIC Cluster

AIC-Based FPGA Architectures

Shadow AIC Architecture

CAD Flow

Conclusion

Embedded Networks-on-Chip for FPGAs

Mohamed Abdelfattah and Vaughn Betz

Introduction

The FPGA Interconnection Challenge

Architecting Embedded NoCs on FPGAs

FabricPort

Designing with Embedded NoCs

Application Case Studies

Related Work

Future Prospects of Embedded NoCs

Design Methodologies for Reconfigurable NoC-Based Embedded Systems

Vincenzo Rana, Francesco Bruchi, Antonio Miele, Marco Santambrogio, and Donatella Sciuto

Introduction

The Proposed Design Flow

Related Work

Algorithm Performance Analysis

Real-World Case Study

Conclusion

Circuits and Architectures for Low-Power FPGAs

Safeen Huda and Jason Anderson

Introduction

Power Consumption in FPGAs

Power and Clock Gating for FPGAs

Multi VDD Architectures

Power Reduction in FPGA Routing Structures

Glitch Reduction

Ultra-Low-Power FPGAs

Examples from Industry

Future Directions

RECONFIGURABLE PROCESSORS

Reconfigurable Processors and Multicore Architectures

Fynn Schwiegelshohn, Philipp Wehner, Jones Mori Alves da Silva, Benedikt Janssen, Osvaldo Navaro Guzman, Jens Rettkowski, Muhammed Al Kadi, Diana Göhringer, and Michael Hübner

Introduction

Reconfigurable Hardware Architectures

Reconfigurable Architectures Management

Conclusion

Partially Reconfigurable Processor for Wireless Receiver Applications

Anupam Chattopadhyay, Gerd Ascheid, Xiaolin Chen, and Zoltán Endre Rákossy

Introduction

Architecture Modeling, Exploration and Implementation Methodology

Case Study: Channel Estimation Architecture

Case Study: Flexible Channel Detection Architecture

Conclusion

APPLICATIONS OF FPGAS AND RECONFIGURABLE SYSTEMS

A Heterogeneous Architecture for Biomolecular Simulation

Christopher Madill, Arun Patel, Manuel Saldãna, Régis Pomés, and Paul Chow

Introduction

Molecular Dynamics

The Toronto Molecular Dynamics Architecture

Results

Conclusion

Design of High-Performance Error-Correcting Codes Using FPGA

Shuanghong Sun and Zhengya Zhang

Introduction

LDPC Code Emulation for Error Floor Exploration

Polar Code Emulation for Optimal Code Construction

Conclusion

Reconfigurable Network Router Security

Russell Tessier, Tilman Wolf, Kekai Hu, and Harikrishnan Chandrikakutty

Introduction

Background

Monitoring System Overview

Monitoring Architectures

Monitoring of FPGA-Based Finite State Machines

Conclusion

EMERGING TECHNOLOGIES

Low-Power FPGAs Based on Resistive Memories

Xifan Tang, Somayyeh Rahimian Omam, Pascal Meinerzhagen,Pierre-Emmanuel Gaillardon, and Giovanni De Micheli

Introduction

Background

Non-Volatile Flip-Flops

Non-Volatile Multiplexers

RRAM-Based FPGA Architecture Performance Predictions

Conclusion

Spintronic-Memory-Based Reconfigurable Computing

Raphael M. Brum, Lionel Torres, and Bojan Jovanović

Introduction

Magnetic Tunnel Junctions

Non-Volatile Memory Circuits

Non-Volatile Elements for FPGAs

Full Non-Volatile FPGA Implementations

Conclusions

Architectures and CAD Tools for 3D FPGAs

Kostas Siozios, Harry Sidiropoulos, and Dimitrios Soudris

Introduction

3-D Reconfigurable Platforms

CAD Algorithms for 3-D Reconfigurable Architectures

Tool Flows Targeting to 3-D FPGAs

Conclusions

About the Editor

Pierre-Emmanuel Gaillardon is a research associate at the Laboratory of Integrated Systems, École Polytechnique Fédérale de Lausanne, Switzerland. He holds an undergraduate degree from École Supérieure de Chimie Physique Électronique de Lyon, France; an M.Sc from Institut National des Sciences Appliquées de Lyon, France; and a Ph.D from Laboratoire d'Électronique des Technologies de l'Information (CEA-LETI), Grenoble, France and the University of Lyon, France. Starting January 2016, he will assume an assistant professorship with the Electrical and Computer Engineering Department, University of Utah, Salt Lake City, USA. Previously, he was a research assistant at CEA-LETI, and a visiting research associate at Stanford University, Palo Alto, California, USA. Dr. Gaillardon is an associate editor of the IEEE Transactions on Nanotechnology, a reviewer for several journals and funding agencies, a technical program committee member for many conferences, and the recipient of the C-Innov 2011 Best Thesis and Nanoarch 2012 Best Paper awards.

About the Series

Devices, Circuits, and Systems

Learn more…

Subject Categories

BISAC Subject Codes/Headings:
TEC007000
TECHNOLOGY & ENGINEERING / Electrical
TEC008000
TECHNOLOGY & ENGINEERING / Electronics / General
TEC008010
TECHNOLOGY & ENGINEERING / Electronics / Circuits / General
TEC061000
TECHNOLOGY & ENGINEERING / Mobile & Wireless Communications