During the last three decades, reconfigurable logic has been growing steadily and can now be found in many different fields. Field programmable gate arrays (FPGAs) are one of the most famous architecture families of reconfigurable devices. FPGAs can be seen as arrays of logic units that can be reconfigured to realize any digital systems. Their high versatility has enabled designers to drastically reduce time to market, and made FPGAs suitable for prototyping or small production series in many branches of industrial products. In addition, and thanks to innovations at the architecture level, FPGAs are now conquering segments of mass markets such as mobile communications.
Reconfigurable Logic: Architecture, Tools, and Applications offers a snapshot of the state of the art of reconfigurable logic systems. Covering a broad range of architectures, tools, and applications, this book:
- Explores classical FPGA architectures and their supporting tools
- Evaluates recent proposals related to FPGA architectures, including the use of network-on-chips (NoCs)
- Examines reconfigurable processors that merge concepts borrowed from the reconfigurable domain into processor design
- Exploits FPGAs for high-performance systems, efficient error correction codes, and high-bandwidth network routers with built-in security
- Expounds on emerging technologies to enhance FPGA architectures, improve routing structures, and create non-volatile configuration flip-flops
Reconfigurable Logic: Architecture, Tools, and Applications reviews current trends in reconfigurable platforms, providing valuable insight into the future potential of reconfigurable systems.
Table of Contents
Adaptive Packing for Design Space Exploration of FPGA Logic Block Architectures. Improving Fault Tolerance of SRAM-Based FPGAs in Harsh Radiation Environments. Zero-Overhead FPGA Debugging. Tree-Based FPGA Routing Architectures. And-Inverter Cones. Embedded Networks-on-Chip for FPGAs. Design Methodologies for Reconfigurable NoC-Based Embedded Systems. Circuits and Architectures for Low-Power FPGAs. Reconfigurable Processors and Multicore Architectures. Partially Reconfigurable Processor for Wireless Receiver Applications. A Heterogeneous Architecture for Biomolecular Simulation. Design of High-Performance Error-Correcting Codes Using FPGA. Reconfigurable Network Router Security. Low-Power FPGAs Based on Resistive Memories. Spintronic-Memory-Based Reconfigurable Computing. Architectures and CAD Tools for 3D FPGAs.
Pierre-Emmanuel Gaillardon is a research associate at the Laboratory of Integrated Systems, École Polytechnique Fédérale de Lausanne, Switzerland. He holds an undergraduate degree from École Supérieure de Chimie Physique Électronique de Lyon, France; an M.Sc from Institut National des Sciences Appliquées de Lyon, France; and a Ph.D from Laboratoire d'Électronique des Technologies de l'Information (CEA-LETI), Grenoble, France and the University of Lyon, France. Starting January 2016, he will assume an assistant professorship with the Electrical and Computer Engineering Department, University of Utah, Salt Lake City, USA. Previously, he was a research assistant at CEA-LETI, and a visiting research associate at Stanford University, Palo Alto, California, USA. Dr. Gaillardon is an associate editor of the IEEE Transactions on Nanotechnology, a reviewer for several journals and funding agencies, a technical program committee member for many conferences, and the recipient of the C-Innov 2011 Best Thesis and Nanoarch 2012 Best Paper awards.