1st Edition
Semiconductors Integrated Circuit Design for Manufacturability
Introduction to DfM
Three Product Questions
SMART Goals
Is/Is Not
Migrating Industrial DfM into IC Manufacturing
The Rule of 10
Concurrent Engineering
Doing it Right the First Time
Product Level DfM
Product Definition
Product architecture
System on Chip vs. System in Package
Design Level DfM
Logical Synthesis
Electrical Models: MOSFETs
Circuits
DfM Metrics
Yield (DfY)
Testability (OfT)
Mask Ratio
Cycletime
DfM Tools
Design Rule Check Engines
IP Management
Conclusions
Biography
Artur Balasinski is a Technology Design Integration Manager for Cypress Semiconductor in San Jose, California. He received the Ph.D.E.E. degree in MOS technology from Warsaw University of Technology, Poland, where he continued as assistant professor. He then joined research team at Yale University, New Haven, CT, to continue – studies on rad-hard devices. Subsequently, he joined the IC industry, first the R&D at STMicroelectronics, working on CMOS process transfers, and since 1997, at Cypress Semiconductor where, as Principal Technology-Design Integration (TDI) engineer, he developed expertise in characterization, process integration, optical proximity correction, and design rules. He has authored or coauthored about 90 papers (3 of them received Best Paper Awards), a book chapter, and has 15 U.S. patents. A member of BACUS Photomask Steering Committee, over the recent years, he attended SPIE, BACUS, VLSI, IEDM conferences where he formulated his views on DfM, as presented in several invited papers and special sessions.






