1st Edition
Stress and Strain Engineering at Nanoscale in Semiconductor Devices
Anticipating a limit to the continuous miniaturization (More-Moore), intense research efforts are being made to co-integrate various functionalities (More-than-Moore) in a single chip. Currently, strain engineering is the main technique used to enhance the performance of advanced semiconductor devices. Written from an engineering applications standpoint, this book encompasses broad areas of semiconductor devices involving the design, simulation, and analysis of Si, heterostructure silicongermanium (SiGe), and III-N compound semiconductor devices. The book provides the background and physical insight needed to understand the new and future developments in the technology CAD (TCAD) design at the nanoscale.
Features
- Covers stressstrain engineering in semiconductor devices, such as FinFETs and III-V Nitride-based devices
- Includes comprehensive mobility model for strained substrates in global and local strain techniques and their implementation in device simulations
- Explains the development of strain/stress relationships and their effects on the band structures of strained substrates
- Uses design of experiments to find the optimum process conditions
- Illustrates the use of TCAD for modeling strain-engineered FinFETs for DC and AC performance predictions
This book is for graduate students and researchers studying solid-state devices and materials, microelectronics, systems and controls, power electronics, nanomaterials, and electronic materials and devices.
Chapter 1. Introduction
1.1 Beyond Silicon
1.2 Towards New Architectures
1.3 Future of nano-CMOS Technology
1.4 Technology CAD
Chapter 2. Simulation Environment
2.1 Synopsys TCAD Tools
2.2 Silvaco TCAD Tools
2.3 VSP Simulation Software
2.4 MINIMOS-NT
2.5 Technology CAD Simulation
2.6 Device Simulation
2.7 Mechanical Stress Modeling
Chapter 3. Stress Generation Techniques in CMOS Technology
Contributed by Dr. S.Das
3.1 Stress/Strain Modeling
3.2 Stress/Strain Mapping in Semiconductor Devices
3.3 Simulation of Deformation
3.4 Epitaxial Layers: Stress Simulation
3.5 Simulation Case Studies
Chapter 4. Electronic Properties of Engineered Substrates
4.1 Energy Gap and Band Structure
4.2 Piezoresistivity Mobility Modeling
4.3 Mobility in a Transistor
4.4 Simulation Case Studies
Chapter 5. Bulk-Si FinFETs
Contributed by Dr. T.P. Das
5.1 Operating Principle
5.2 FinFETs: Scaling and Design Issues
5.3 Virtual Fabrication of Bulk-Si TriGate FinFETs
5.4 Stress Tuning using epi-SiGe Source/Darin Stressor
5.5 Electrical Performance
Chapter 6. Strain-Engineered FinFETs at NanoScale
Contributed by Dr. T.P. Das
6.1 Design and Simulation at 7N
6.2 Design Issues
6.3 Variability Due to Geometry Change
6.4 Variability Due to Metal Grain Granularity
6.5 Variability due to Random Discrete Dopants
Chapter 7. Technology CAD of III-Nitride Based Devices
7.1 History of Nitride Technology
7.2 Material Properties III-N
7.3 Optical properties
7.4 Polarization in Nitride Semiconductors
7.5 HEMT Structure
7.6 Simulation Case Studies
Chapter 8. Strain-Engineered SiGe Channel TFT for Flexible Electronics
8.1 Heteroepitaxy of Si-Ge Layers
8.2 Device Structure Generation
8.3 Stress Analysis
8.4 Device Simulation
Biography
Professor Chinmay K. Maiti, PhD is an Ex-Professor and Ex-Head of Department from Indian Institute of Technology (IIT) – Kharagpur, India. He then joined the SOA University, Bhubaneswar in May 2015 as a Professor, where he is now on a Visiting Assignment. He is interested in strain-engineering in nanodevices, flexible electronics, and semiconductor device/process simulation research, and microelectronics education. He has published several monographs in Silicon-Germanium, heterostructure-Silicon, and Technology CAD areas. He has edited the "Selected Works of Professor Herbert Kroemer", World Scientific, Singapore, 2008.
