The VLSI Handbook: 2nd Edition (Hardback) book cover

The VLSI Handbook

2nd Edition

Edited by Wai-Kai Chen

CRC Press

2,320 pages | 1827 B/W Illus.

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Hardback: 9780849341991
pub: 2006-12-26
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Description

For the new millenium, Wai-Kai Chen introduced a monumental reference for the design, analysis, and prediction of VLSI circuits: The VLSI Handbook. Still a valuable tool for dealing with the most dynamic field in engineering, this second edition includes 13 sections comprising nearly 100 chapters focused on the key concepts, models, and equations.

Written by a stellar international panel of expert contributors, this handbook is a reliable, comprehensive resource for real answers to practical problems. It emphasizes fundamental theory underlying professional applications and also reflects key areas of industrial and research focus.

WHAT'S IN THE SECOND EDITION?

Sections on…

  • Low-power electronics and design
  • VLSI signal processing

Chapters on…

  • CMOS fabrication
  • Content-addressable memory
  • Compound semiconductor RF circuits
  • High-speed circuit design principles
  • SiGe HBT technology
  • Bipolar junction transistor amplifiers
  • Performance modeling and analysis using SystemC
  • Design languages, expanded from two chapters to twelve
  • Testing of digital systems

Structured for convenient navigation and loaded with practical solutions, The VLSI Handbook, Second Edition remains the first choice for answers to the problems and challenges faced daily in engineering practice.

Reviews

"It is easily the most complete source of information on VLSI available."

– Books-On-Line, March 2007

Table of Contents

VLSI TECHNOLOGY

Bipolar Technology; B. Gunnar Malm, Jan V. Grahn and Mikael Östling

CMOS/BiCMOS Technology; Yasuhiro Katsumata, Tatsuya Ohguro, Kazumi Inoh, Eiji Morifuji, Takashi Yoshitomi, Hideki Kimijima, Hideaki Nii, Toyota Morimoto, Hisayo S. Momose, Kuniyoshi Yoshikawa, Hidemi Ishiuchi and Hiroshi Iwai

Silicon-On-Insulator Technology; Sorin Cristoloveanu

SiGe HBT Technology; John D. Cressler

Silicon Carbide Technology; Philip G. Neudeck

Passive Components; Ashraf Lotfi

Power IC Technologies; Akio Nakagawa

Microelectronics Packaging; Bi-Shiou Chiou

Multichip Module Technologies; Victor Boyadzhyan and

John Choma, Jr.

DEVICES AND THEIR MODELS

Bipolar Junction Transistor Circuits; David J. Comer and Donald T. Comer

RF Passive IC Components; Thomas H. Lee, Maria del Mar Hershenson, Sunderarajan S. Mohan, Kirad Samavati and C. Patrick Yue

CMOS Fabrication; Jeff Jessing

Analog Circuit Simulation; J. Gregory Rollins

Interconnect Modeling and Simulation; Michel S. Nakhla and Ramachandra Achar

LOW POWER ELECTRONICS AND DESIGN

System-Level Power Management: An Overview; Ali Iranli and Massoud Pedram

Communication-Based Design for Nanoscale SoCs; Umit Y. Ogras and Radu Marculescu

Power-Aware Architectural Synthesis; Robert P. Dick, Li Shang and Niraj K. Jha

Dynamic Voltage Scaling for Low-Power Hard Real-Time Systems; Jihong Kim, Flavius Gruian and Dongkun Shin

Low-Power Microarchitecture Techniques and Compiler Design Techniques; Emil Talpes and Diana Marculescu

Architecture and Design Flow Optimizations for Power-Aware FPGAs; Aman Gayasen and Narayanan Vijaykrishnan

Technology Scaling and Low-Power Circuit Design; Ali Keshavarzi

AMPLIFIERS

CMOS Amplifier Design; Harry W. Li, R. Jacob Baker and Donald C. Thelen

Bipolar Junction Transistor Amplifiers; David J. Comer and Donald T. Comer

High-Frequency Amplifiers; Chris Toumazou and Alison Burdett

Operational Transconductance Amplifiers; Mohammed Ismail, Seok-Bae Park, Ayman A. Fayed and R.F. Wassenaar

LOGIC CIRCUITS

Expressions of Logic Functions; Saburo Muroga

Basic Theory of Logic Functions; Saburo Muroga

Simplification of Logic Expressions; Saburo Muroga

Binary Decision Diagrams; Shin-ichi Minato and Saburo Muroga

Logic Synthesis with AND and OR Gates in Two Levels; Saburo Muroga

Sequential Networks; Saburo Muroga

Logic Synthesis with AND and OR Gates in Multi-Levels; Yuichi Nakamura and Saburo Muroga

Logic Properties of Transistor Circuits; Saburo Muroga

Logic Synthesis with NAND (or NOR) Gates in Multi-Levels; Saburo Muroga

Logic Synthesis with a Minimum Number of Negative Gates; Saburo Muroga

Logic Synthesizer with Optimizations in Two Phases; Ko Yoshikawa and Saburo Muroga

Logic Synthesizer by the Transduction Method; Saburo Muroga

Emitter-Coupled Logic; Saburo Muroga

CMOS; Saburo Muroga

Pass Transistors; Kazuo Yano and Saburo Muroga

Adders; Naofumi Takagi, Haruyuki Tago, Charles R. Baugh and Saburo Muroga

Multipliers; Naofumi Takagi, Charles R. Baugh and Saburo Muroga

Dividers; Naofumi Takagi and Saburo Muroga

Full-Custom and Semi-Custom Design; Saburo Muroga

Programmable Logic Devices; Saburo Muroga

Gate Arrays; Saburo Muroga

Field-Programmable Gate Arrays; Saburo Muroga

Cell-Library Design Approach; Saburo Muroga

Comparison of Different Design Approaches; Saburo Muroga

MEMORY, REGISTERS AND SYSTEM TIMING

System Timing; Baris Taskin, Ivan S. Kourtev and Eby G. Friedman

ROM/PROM/EPROM; Jen-Sheng Hwang

SRAM; Yuh-Kuang Tseng

Embedded Memory; Chung-Yu Wu

Flash Memories; Rick Shih-Jye Shen, Frank Ruei-Ling Lin, Amy Hsiu-Fen Chou, Evans Ching-Song Yang and Charles Ching-Hsiang Hsu

Dynamic Random Access Memory; Kuo-Hsing Cheng

Content-Addressable Memory; Chi-Sheng Lin and Bin-Da Liu

Low-Power Memory Circuits; Martin Margala

ANALOG CIRCUITS

Nyquist-Rate ADC and DAC; Bang-Sup Song

Oversampled Analog-to-Digital and Digital-to-Analog Converters; John W. Fattaruso and Louis A. Williams III

RF Communication Circuits; Michiel Steyaert, Wouter De Cock and Patrick Reynaert

PLL Circuits; Muh-Tian Shiue and Chorng-kuang Wang

Switched-Capacitor Filters; Andrea Baschirotto

MICROPROCESSOR AND ASIC

Timing and Signal Integrity Analysis; Abhijit Dharchoudhury, David Blaauw and Shantanu Ganguly

Microprocessor Design Verification; Vikram Iyengar

Microprocessor Layout Method; Tanay Karnik

Architecture; Daniel A. Connors and Wen-mei W. Hwu

Logic Synthesis for Field Programmable Gate Array (FPGA) Technology; John Lockwood

TESTING OF DIGITAL SYSTEMS

Design for Testability and Test Architectures; Dimitri Kagaris, Nick Kanopoulos and Spyros Tragoudas

Automatic Test Pattern Generation; Spyros Tragoudas

Built-In Self Test; Dimitri Kagaris

COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT TECHNOLOGY

Compound Semiconductor Materials; Stephen I. Long

Compound Semiconductor Devices for Analog and Digital Circuits; Donald B. Estreich

Compound Semiconductor RF Circuits; Donald B. Estreich

High-Speed Circuit Design Principles; Stephen I. Long

DESIGN AUTOMATION

Internet-Based Micro-Electronic Design Automation (IMEDA) Framework; Moon Jung Chung and Heechul Kim

System-Level Design; Alice C. Parker, Yosef Tirat-Gefen and Suhrid A. Wadekar

Performance Modeling and Analysis Using VHDL and SystemC; Robert H. Klenke, Jonathan A. Andrews and James H. Aylor

Embedded Computing Systems and Hardware/Software Co-Design; Wayne Wolf

Design Automation Technology Roadmap; Donald R. Cottrell

VLSI SIGNAL PROCESSING

Computer Arithmetic for VLSI Signal Processing; Earl E. Swartzlander Jr.

VLSI Architectures for JPEG 2000 EBCOT: Design Techniques and Challenges; Yijun Li and Magdy Bayoumi

VLSI Architectures for Forward Error-Control Decoders; Arshad Ahmed, Seok-Jun Lee, Mohammad Mansour and Naresh R. Shanbhag

An Exploration of Hardware Architectures for Face Detection; T. Theocharides, C. Nicopoulos, K. Irick, N. Vijaykrishnan and M.J. Irwin

Multidimensional Logarithmic Number System; Roberto Muscedere, Vassil S. Dimitrov and Graham A. Jullien

DESIGN LANGUAGES

Languages for Design and Implementation of Hardware; Zainalabedin Navabi

System Level Design Languages; Shahrzad Mirkhani and Zainalabedin Navabi

RT Level Hardware Description with VHDL; Mahsan Rofouei and Zainalabedin Navabi

Register Transfer Level Hardware Description with Verilog; Zainalabedin Navabi

Register-Transfer Level Hardware Description with SystemC; Shahrzad Mirkhani and Zainalabedin Navabi

System Verilog; Saeed Safari

VHDL-AMS Hardware Description Language; Naghmeh Karimi and Zainalabedin Navabi

Verification Languages; Hamid Shojaei and Zainalabedin Navabi

ASIC and Custom IC Cell Information Representation; Naghmeh Karimi and Zainalabedin Navabi

Test Languages; Shahrzad Mirkhani and Zainalabedin Navabi

Timing Description Languages; Naghmeh Karimi and Zainalabedin Navabi

HDL-Based Tools and Environments; Saeed Safari

Index

About the Originator

About the Series

Electrical Engineering Handbook

Learn more…

Subject Categories

BISAC Subject Codes/Headings:
COM059000
COMPUTERS / Computer Engineering
TEC008000
TECHNOLOGY & ENGINEERING / Electronics / General
TEC008010
TECHNOLOGY & ENGINEERING / Electronics / Circuits / General