Introduction to Verilog HDL
Built-In Primitives
User-Defined Primitives
Dataflow Modeling
Behavioral Modeling
Structural Modeling
Problems
Synthesis of Synchronous Sequential Machines 1 Using Verilog HDL
Synchronous Registers
Synchronous Counters
Moore Machines
Mealy Machines
Moore–Mealy Equivalence
Output Glitches
Problems
Synthesis of Synchronous Sequential Machines 2 Using Verilog HDL
Multiplexers for δ Next-State Logic
Decoders for λ Output Logic
Programmable Logic Devices
Iterative Networks
Error Detection in Synchronous Sequential Machines
Problems
Synthesis of Asynchronous Sequential Machines Using Verilog HDL
Introduction
Synthesis Examples
Problems
Synthesis of Pulse-Mode Asynchronous Sequential Machines Using Verilog HDL
Introduction
Synthesis Examples
Problems
Appendix A: Event Queue
Appendix B: Verilog Project Procedure
Appendix C: Answers to Select Problems
Biography
Joseph Cavanagh is an adjunct professor in the Computer Engineering Department at Santa Clara University, California, USA. He is the author of several textbooks, including Computer Arithmetic and Verilog HDL Fundamentals (2009), Digital Design and Verilog HDL Fundamentals (2008), Verilog HDL: Digital Design and Modeling (2007), and Sequential Logic: Analysis and Synthesis (2006), as well as a novel, The Computer Conspiracy.
"… thorough coverage of counter design. … [a] good introductory text for Verilog."
—Parag K. Lala, Texas A&M University-Texarkana, USA"For the reader looking to succeed with understanding both the foundation of the principles of sequential logic along with the ability to apply these principles using Verilog HDL, this text is a guarantee to achieve those goals."
—Geri Lamble, Santa Clara University, California, USA
