386 Pages
158 B/W Illustrations
by
CRC Press
392 Pages
158 B/W Illustrations
by
CRC Press
Also available as eBook on:
Which came first, the system or the chip? While integrated circuits enable technology for the modern information age, computing, communication, and network chips fuel it. As soon as the integration ability of modern semiconductor technology offers presents opportunities, issues in power consumption, reliability, and form-factor present challenges. The demands of emerging software applications can... Read more
Architecture and Implementation of the TRIPS Processor, S.W. Keckler, D. Burger, K. Sankaralingam, R. Nagarajan, R. McDonald, R. Desikan, S. Drolia, M.S. Govindan, P. Gratz, D. Gulati, H. Hanson, C. Kim, H. Liu, N. Ranganathan, S. Sethumadhavan, S. Sharif, and P. Shivakumar
High -Performance Data Security in an x86 Processor, G. Henry, T. Parks, and T. Crispin
ARM Cortex A8: A High Performance Processor for Low Power Applications, D. Williamson
Rotated Array Clustered Extended Hypercube Processor: The RACE-H Processor, G.G. Pechanek, M. Stojancic, F. Barry, and N. Pitsianis
A High-Throughput Self-Timed FPGA Core Architecture, B.C. Gaide and L.K John
The Continuation Based Multithreading Processor, M. Izumi, S. Amamiya, T. Matsuzaki, and M. Amamiya
A Study of a Processor with Dual Thread Execution Modes, R. Mameesh and M. Franklin
Measurement Based Power Phase Analysis, W.L. Bircher and L.K. John
Visualization by Subdivision: Two Applications for Future Graphics Platforms, C.T. John
A Performance Analysis of Two-level Heterogeneous Systems on Wavefront Algorithms, D.J. Kerbyson and A. Hoisie
Microarchitectural Characteristics and Implications of Alignment of Multiple Bioinformatics Sequences, T. Li
Towards System-Level Fault-Tolerance Using Formal Methods and SoC Methodologies Evaluation of Delay Queues for a Ravenscar Kernel, K. Lundqvist
Forward Error Correction for On-chip Interconnection Networks, P. Bhojwani, R. Singhal, G. Choi, and R. Mahapatra
Alleviating Thermal Constraints while Maintaining Performance via Silicon-based On-Chip Optical Interconnects, N. Nelson, G. Briggs, M. Haurylau, G. Chen, H. Cgen, D.H. Albonesi, E.G. Friedman, and P.M. Fauchet
High -Performance Data Security in an x86 Processor, G. Henry, T. Parks, and T. Crispin
ARM Cortex A8: A High Performance Processor for Low Power Applications, D. Williamson
Rotated Array Clustered Extended Hypercube Processor: The RACE-H Processor, G.G. Pechanek, M. Stojancic, F. Barry, and N. Pitsianis
A High-Throughput Self-Timed FPGA Core Architecture, B.C. Gaide and L.K John
The Continuation Based Multithreading Processor, M. Izumi, S. Amamiya, T. Matsuzaki, and M. Amamiya
A Study of a Processor with Dual Thread Execution Modes, R. Mameesh and M. Franklin
Measurement Based Power Phase Analysis, W.L. Bircher and L.K. John
Visualization by Subdivision: Two Applications for Future Graphics Platforms, C.T. John
A Performance Analysis of Two-level Heterogeneous Systems on Wavefront Algorithms, D.J. Kerbyson and A. Hoisie
Microarchitectural Characteristics and Implications of Alignment of Multiple Bioinformatics Sequences, T. Li
Towards System-Level Fault-Tolerance Using Formal Methods and SoC Methodologies Evaluation of Delay Queues for a Ravenscar Kernel, K. Lundqvist
Forward Error Correction for On-chip Interconnection Networks, P. Bhojwani, R. Singhal, G. Choi, and R. Mahapatra
Alleviating Thermal Constraints while Maintaining Performance via Silicon-based On-Chip Optical Interconnects, N. Nelson, G. Briggs, M. Haurylau, G. Chen, H. Cgen, D.H. Albonesi, E.G. Friedman, and P.M. Fauchet
Biography
Eugene John, Juan Rubio
