1st Edition

Low-Power NoC for High-Performance SoC Design

By Hoi-Jun Yoo, Kangmin Lee, Jun Kyong Kim Copyright 2008
    300 Pages 270 B/W Illustrations
    by CRC Press

    Chip Design and Implementation from a Practical Viewpoint

    Focusing on chip implementation, Low-Power NoC for High-Performance SoC Design provides practical knowledge and real examples of how to use network on chip (NoC) in the design of system on chip (SoC). It discusses many architectural and theoretical studies on NoCs, including design methodology, topology exploration, quality-of-service guarantee, low-power design, and implementation trials.

    The Steps to Implement NoC

    The book covers the full spectrum of the subject, from theory to actual chip design using NoC. Employing the Unified Modeling Language (UML) throughout, it presents complicated concepts, such as models of computation and communication–computation partitioning, in a manner accessible to laypeople. The authors provide guidelines on how to simplify complex networking theory to design a working chip. In addition, they explore the novel NoC techniques and implementations of the Basic On-Chip Network (BONE) project. Examples of real-time decisions, circuit-level design, systems, and chips give the material a real-world context.

    Low-Power NoC and Its Application to SoC Design

    Emphasizing the application of NoC to SoC design, this book shows how to build the complicated interconnections on SoC while keeping a low power consumption.

    Preface NoC-Based System-Level Design
    NoC and System-Level Design
    Introduction to SoC Design
    Platform-Based SoC Design
    Multiprocessor SoC and NoC
    Low-Power SoC Design
    System Design with Model of Computation
    System Models
    Validation and Verification
    Hardware/Software Codesign
    Application Analysis
    Computation–Communication Partitioning
    Communication System: Current Trend
    Separation of Communication and Computation
    Communication-Centric SoC Design
    Communication Synthesis
    Network-Based Design
    NoC-Based real Chip Implementation
    NoC-Based SoC
    Architecture of NoC
    Practical Design of NoC
    NoC Topology and Protocol Design
    Analysis Methodology
    Energy Exploration
    NoC Protocol Design
    Low Power Design for NoC
    Low-Power Signaling
    On-Chip Serialization
    Low-Power Clocking
    Low-Power Channel Coding
    Low-Power Switch
    Low-Power NoC Protocol
    Real Chip Implementation
    BONE Series
    Industrial Implementations
    Academic Implementations
    Appendix: BONE Protocol Specification
    Overview of BONE
    BONE Protocol
    References appear at the end of each chapter.


    Hoi-Jun Yoo, Kangmin Lee, Jun Kyong Kim